/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfoXCV.td | 30 class CVBitManipRR<bits<7> funct7, string opcodestr> 34 class CVBitManipR<bits<7> funct7, string opcodestr> 43 def CV_EXTRACT : CVBitManipRII<0b00, 0b000, "cv.extract">; 44 def CV_EXTRACTU : CVBitManipRII<0b01, 0b000, "cv.extractu">; 54 def CV_INSERT : CVInstBitManipRII<0b10, 0b000, (outs GPR:$rd_wb), 72 class CVInstMac<bits<7> funct7, bits<3> funct3, string opcodestr> 175 class CVInstAluRR<bits<7> funct7, bits<3> funct3, string opcodestr> 179 class CVInstAluRRNR<bits<7> funct7, bits<3> funct3, string opcodestr> 183 class CVInstAluRI<bits<7> funct7, bits<3> funct3, string opcodestr> 193 class CVInstAluR<bits<7> funct [all...] |
H A D | RISCVInstrInfoZk.td | 62 : RVInstR<{0b00, funct5}, 0b000, OPC_OP, (outs GPR:$rd), 70 class RVKUnary_rnum<bits<7> funct7, bits<3> funct3, string opcodestr> 88 def AES64DS : ALU_rr<0b0011101, 0b000, "aes64ds">; 89 def AES64DSM : ALU_rr<0b0011111, 0b000, "aes64dsm">; 95 def AES64KS2 : ALU_rr<0b0111111, 0b000, "aes64ks2">; 106 def AES64ES : ALU_rr<0b0011001, 0b000, "aes64es">; 107 def AES64ESM : ALU_rr<0b0011011, 0b000, "aes64esm">; 118 def SHA512SIG0H : ALU_rr<0b0101110, 0b000, "sha512sig0h">; 119 def SHA512SIG0L : ALU_rr<0b0101010, 0b000, "sha512sig0l">; 120 def SHA512SIG1H : ALU_rr<0b0101111, 0b000, "sha512sig1 [all...] |
H A D | RISCVInstrInfoZfa.td | 49 class FPBinaryOp_rr<bits<7> funct7, bits<3> funct3, DAGOperand rdty, 55 class FPFLI_r<bits<7> funct7, bits<5> rs2val, bits<3> funct3, 67 class FPUnaryOp_r_rtz<bits<7> funct7, bits<5> rs2val, DAGOperand rdty, 81 def FLI_S : FPFLI_r<0b1111000, 0b00001, 0b000, FPR32, "fli.s">, 102 def FLI_D : FPFLI_r<0b1111001, 0b00001, 0b000, FPR64, "fli.d">, 128 def FMVH_X_D : FPUnaryOp_r<0b1110001, 0b00001, 0b000, GPR, FPR64, "fmvh.x.d">, 130 def FMVP_D_X : FPBinaryOp_rr<0b1011001, 0b000, FPR64, GPR, "fmvp.d.x">, 135 def FMV_X_W_FPR64 : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR64, 142 def FLI_H : FPFLI_r<0b1111010, 0b00001, 0b000, FPR16, "fli.h">,
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H A D | RISCVInstrInfoC.td | 98 // A 7-bit unsigned immediate where the least significant two bits are zero. 101 let ParserMatchClass = UImmAsmOperand<7, "Lsb00">; 103 let DecoderMethod = "decodeUImmOperand<7>"; 272 let Inst{12} = imm{7}; 297 let Inst{9-7} = rd; 307 def C_ADDI4SPN : RVInst16CIW<0b000, 0b00, (outs GPRC:$rd), 313 let Inst{10-7} = imm{9-6}; 323 let Inst{6-5} = imm{7-6}; 328 bits<7> imm; 338 bits<7> imm; [all …]
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H A D | RISCVInstrInfoF.td | 137 // doesn't affect the output originally always set it to 0b000 ('rne'). As old 190 class FPALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr, 196 multiclass FPALU_rr_m<bits<7> funct7, bits<3> funct3, string opcodestr, 204 class FPALU_rr_frm<bits<7> funct7, string opcodestr, DAGOperand rty, 211 multiclass FPALU_rr_frm_m<bits<7> funct7, string opcodestr, 218 class FPUnaryOp_r<bits<7> funct7, bits<5> rs2val, bits<3> funct3, 224 multiclass FPUnaryOp_r_m<bits<7> funct7, bits<5> rs2val, bits<3> funct3, 233 class FPUnaryOp_r_frm<bits<7> funct7, bits<5> rs2val, DAGOperand rdty, 240 multiclass FPUnaryOp_r_frm_m<bits<7> funct7, bits<5> rs2val, 251 class FPUnaryOp_r_frmlegacy<bits<7> funct7, bits<5> rs2val, DAGOperand rdty, [all …]
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H A D | RISCVInstrInfo.td | 231 def uimm7_opcode : RISCVUImmOp<7> { 234 def uimm7 : RISCVUImmOp<7>; 521 class HLoad_r<bits<7> funct7, bits<5> funct5, string opcodestr> 537 class HStore_rr<bits<7> funct7, string opcodestr> 559 class ALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr, 580 class ShiftW_ri<bits<7> imm11_5, bits<3> funct3, string opcodestr> 587 class ALUW_rr<bits<7> funct7, bits<3> funct3, string opcodestr, 595 class Priv<string opcodestr, bits<7> funct7> 596 : RVInstR<funct7, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1, GPR:$rs2), 600 class Priv_rr<string opcodestr, bits<7> funct7> [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64SystemOperands.td | 52 let Encoding{10-7} = crn; 58 def : AT<"S1E1R", 0b000, 0b0111, 0b1000, 0b000>; 59 def : AT<"S1E2R", 0b100, 0b0111, 0b1000, 0b000>; 60 def : AT<"S1E3R", 0b110, 0b0111, 0b1000, 0b000>; 61 def : AT<"S1E1W", 0b000, 0b0111, 0b1000, 0b001>; 64 def : AT<"S1E0R", 0b000, 0b0111, 0b1000, 0b010>; 65 def : AT<"S1E0W", 0b000, 0b0111, 0b1000, 0b011>; 72 def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>; 73 def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>; 77 def : AT<"S1E1A", 0b000, 0b0111, 0b1001, 0b010>; [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonDepInstrInfo.td | 48 let Inst{7-5} = 0b000; 64 let Inst{7-5} = 0b011; 76 let Inst{7-5} = 0b010; 88 let Inst{7-5} = 0b001; 100 let Inst{7-5} = 0b000; 112 let Inst{7-5} = 0b111; 125 let Inst{7-5} = 0b110; 138 let Inst{7 [all...] |
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
H A D | M68kInstrArithmetic.td | 38 def MxOpMode8_d_EA : MxOpModeEncoding<0b000>; 61 /// F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 78 !eq(SRC_TYPE.RLet, "d") : (descend 0b000, (operand "$opd", 3)) 97 /*MODE*/0b000, 117 /// F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0 154 /*MODE*/0b000, 327 /// F E D C | B A 9 | 8 | 7 6 | 5 4 | 3 | 2 1 0 423 /*MODE*/0b000, 533 /// F E D C B A 9 | 8 7 6 | 5 4 3 | 2 1 0 552 0b000, [all …]
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/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
H A D | RISCVCInstructions.h | 40 constexpr RxC DecodeCA_RD(uint32_t inst) { return RxC{(inst & 0x380) >> 7}; } in DecodeCA_RD() 54 uint16_t offset = ((inst << 4) & 0xc0) // offset[7:6] in DecodeC_LWSP() 55 | ((inst >> 7) & 0x20) // offset[5] in DecodeC_LWSP() 65 | ((inst >> 7) & 0x20) // offset[5] in DecodeC_LDSP() 73 uint16_t offset = ((inst >> 1) & 0xc0) // offset[7:6] in DecodeC_SWSP() 74 | ((inst >> 7) & 0x3c); // offset[5:2] in DecodeC_SWSP() 80 | ((inst >> 7) & 0x38); // offset[5:3] in DecodeC_SDSP() 86 | ((inst >> 7) & 0x38) // imm[5:3] in DecodeC_LW() 92 uint16_t offset = ((inst << 1) & 0xc0) // imm[7:6] in DecodeC_LD() 93 | ((inst >> 7) & 0x38); // imm[5:3] in DecodeC_LD() [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
H A D | pmk8350.dtsi | 88 bits = <1 7>; 92 pmk8350_gpios: gpio@b000 {
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsMSAInstrInfo.td | 390 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>; 391 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>; 392 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>; 393 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>; 410 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>; 411 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>; 412 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>; 413 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>; 415 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>; 416 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>; [all …]
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H A D | MipsMSAInstrFormats.td | 438 let Inst{10-8} = 0b000; 439 let Inst{7-6} = sa; 452 let Inst{10-8} = 0b000; 453 let Inst{7-6} = sa;
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/freebsd/sys/contrib/device-tree/src/riscv/sophgo/ |
H A D | sg2042.dtsi | 146 gpio2: gpio@703000b000 { 271 interrupts-extended = <&cpu0_intc 7>, 272 <&cpu1_intc 7>, 273 <&cpu2_intc 7>, 274 <&cpu3_intc 7>; 281 interrupts-extended = <&cpu4_intc 7>, 282 <&cpu5_intc 7>, 283 <&cpu6_intc 7>, 284 <&cpu7_intc 7>; 291 interrupts-extended = <&cpu8_intc 7>, [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMInstrThumb2.td | 326 let EncoderMethod = "getT2ScaledImmOpValue<7,2>"; 451 let Inst{7-0} = imm{7-0}; 465 let Inst{7-0} = imm{7-0}; 477 let Inst{7-0} = imm{7-0}; 491 let Inst{7-6} = ShiftedRm{8-7}; 504 let Inst{7-6} = ShiftedRm{8-7}; 517 let Inst{7-6} = ShiftedRm{8-7}; 562 let Inst{7-0} = imm{7-0}; 576 let Inst{7-0} = imm{7-0}; 589 let Inst{7-6} = imm{1-0}; [all …]
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/freebsd/sys/contrib/device-tree/src/arm/arm/ |
H A D | versatile-pb.dts | 58 interrupt-map-mask = <0x1800 0 0 7>; 104 mmc@b000 {
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/freebsd/sys/dts/arm/ |
H A D | vybrid.dtsi | 81 ccm@4006b000 { 247 7 0x200060 >; 258 7 0x200060 >; 435 adc0: adc@4003B000 {
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/freebsd/sys/contrib/device-tree/src/arm/hisilicon/ |
H A D | hi3620.dtsi | 149 interrupts = <0 6 4>, <0 7 4>; 227 &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>; 242 &pmx0 6 5 1 &pmx0 7 6 1>; 255 gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1 257 &pmx0 6 3 1 &pmx0 7 3 1>; 272 &pmx0 6 11 1 &pmx0 7 11 1>; 287 &pmx0 6 13 1 &pmx0 7 13 1>; 294 gpio5: gpio@80b000 { 302 &pmx0 6 16 1 &pmx0 7 16 1>; 317 &pmx0 6 18 1 &pmx0 7 19 1>; [all …]
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/freebsd/sys/contrib/alpine-hal/ |
H A D | al_hal_serdes_interface.h | 74 AL_SRDS_REG_PAGE_0123_LANES_0123 = 7, 238 * -3'b000: -3dB 249 * -3'b000: 684MHz 267 * 7: -105mVpeak 298 * -4'b0001: +7mVpeak 303 * -4'b1001: -7mVpeak 323 * -3'b000: Disconnected
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
H A D | imx27.dtsi | 180 uart2: serial@1000b000 { 275 dmas = <&dma 7>; 404 uart5: serial@1001b000 { 550 fec: ethernet@1002b000 {
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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/ |
H A D | mpc8536ds.dtsi | 71 partition@7f00000 { 76 partition@7f80000 { 240 usb@2b000 {
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/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/ |
H A D | vfxxx.dtsi | 136 dmas = <&edma0 0 6>, <&edma0 0 7>; 266 adc0: adc@4003b000 { 334 gpio2: gpio@4004b000 { 364 gpio-ranges = <&iomuxc 0 128 7>; 428 clks: ccm@4006b000 {
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
H A D | mediatek,mt8365-pinctrl.yaml | 143 7: (E1, E0, EN) = (1, 1, 1) 144 So the valid arguments are from 0 to 7. 146 enum: [0, 1, 2, 3, 4, 5, 6, 7] 212 pio: pinctrl@1000b000 {
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCInstrInfo.td | 523 def SP_ADD_SP_S : F16_SP_OPS_bconst<0b000, "add_s">; 525 (outs GPR32Reduced:$b3), (ins immU<7>:$u7), 528 def SP_LD_S : F16_SP_LD<0b000, "ld_s">; 534 (outs), (ins immU<7>:$u7), "leave_s\t$u7"> { 536 bits<7> u7; 568 let Inst{7-5} = LImmReg{2-0}; 661 let Inst{7-0} = u10{9-2}; 680 def BGT_S : F16_BCC_s7<0b000, "bgt_s">; 714 def ASL_S_ru5 : F16_SH_SUB_BIT_DST<0b000,"asl_s">; 727 F16_OP_HREG_LIMM<0b000, (outs GPR32:$b_s3), (ins i32imm:$LImm), [all …]
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/freebsd/sys/contrib/device-tree/src/arm/broadcom/ |
H A D | bcm53573.dtsi | 102 <0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 244 gmac1: ethernet@b000 {
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