| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-rgb.rst | 10 These formats encode each pixel as a triplet of RGB values. They are packed
13 bits required to store a pixel is not aligned to a byte boundary, the data is
21 or a permutation thereof, collectively referred to as alpha formats) depend on
25 a meaningful value. Otherwise, when the device doesn't capture an alpha channel
26 but can set the alpha bit to a user-configurable value, the
29 the value specified by that control. Otherwise a corresponding format without
35 filled with meaningful values by applications. Otherwise a corresponding format
39 Formats that contain padding bits are named XRGB (or a permutation thereof).
45 - In all the tables that follow, bit 7 is the most significant bit in a byte.
47 respectively. 'a' denotes bits of the alpha component (if supported by the
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| H A D | pixfmt-packed-yuv.rst | 16 - In all the tables that follow, bit 7 is the most significant bit in a byte.
18 'U') and red chroma (also known as 'V') components respectively. 'A'
26 These formats do not subsample the chroma components and store each pixels as a
31 seen in a 16-bit word, which is then stored in memory in little endian byte
33 format stores a pixel in a 16-bit word [15:0] laid out at as [Y'\ :sub:`4-0`
52 - :cspan:`7` Byte 0 in memory
54 - :cspan:`7` Byte 1
58 - 7
67 - 7
90 - a\ :sub:`3`
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| /linux/sound/usb/caiaq/ |
| H A D | control.c | 181 { "LED 7seg_1b", 8 },
182 { "LED 7seg_1c", 9 },
183 { "LED 7seg_2a", 10 },
184 { "LED 7seg_2b", 11 },
185 { "LED 7seg_2c", 12 },
186 { "LED 7seg_2d", 13 },
187 { "LED 7seg_2e", 14 },
188 { "LED 7seg_2f", 15 },
189 { "LED 7seg_2g", 16 },
190 { "LED 7seg_3a", 17 },
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| /linux/tools/perf/pmu-events/arch/x86/arrowlake/ |
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
24 "Counter": "0,1,2,3,4,5,6,7",
27 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
33 "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
51 "BriefDescription": "Counts the number of BACLEARS due to a return branch.",
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| H A D | virtual-memory.json | 3 …"BriefDescription": "Counts the number of page walks initiated by a demand load that missed the fi…
4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
21 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
22 "Counter": "0,1,2,3,4,5,6,7",
31 "Counter": "0,1,2,3,4,5,6,7,8,9",
40 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
41 "Counter": "0,1,2,3,4,5,6,7",
49 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
50 "Counter": "0,1,2,3,4,5,6,7,8,9",
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| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
25 "Counter": "0,1,2,3,4,5,6,7",
35 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7,8,9",
56 "Counter": "0,1,2,3,4,5,6,7",
65 "Counter": "0,1,2,3,4,5,6,7",
73 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
74 "Counter": "0,1,2,3,4,5,6,7,8,9",
77 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
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| H A D | other.json | 3 …re not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and…
4 "Counter": "0,1,2,3,4,5,6,7,8,9",
7 …re not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
22 …"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to a lock In Progr…
23 "Counter": "0,1,2,3,4,5,6,7",
26 …Counts the number of unhalted cycles a Core is blocked due to a lock In Progress issued by another…
32 …"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to an Accepted loc…
33 "Counter": "0,1,2,3,4,5,6,7",
36 …r of unhalted cycles a Core is blocked due to an Accepted lock it issued, includes both split and …
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/lunarlake/ |
| H A D | virtual-memory.json | 3 …"BriefDescription": "Counts the number of page walks initiated by a demand load that missed the fi…
4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
21 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
22 "Counter": "0,1,2,3,4,5,6,7",
31 "Counter": "0,1,2,3,4,5,6,7,8,9",
40 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
41 "Counter": "0,1,2,3,4,5,6,7,8,9",
45 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
52 "Counter": "0,1,2,3,4,5,6,7",
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| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
23 "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
24 "Counter": "0,1,2,3,4,5,6,7",
33 "Counter": "0,1,2,3,4,5,6,7",
41 "BriefDescription": "Counts the number of BACLEARS due to a return branch.",
42 "Counter": "0,1,2,3,4,5,6,7",
50 "BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.",
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| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
25 "Counter": "0,1,2,3,4,5,6,7",
35 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
55 "Counter": "0,1,2,3,4,5,6,7,8,9",
66 "Counter": "0,1,2,3,4,5,6,7",
75 "Counter": "0,1,2,3,4,5,6,7",
83 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
84 "Counter": "0,1,2,3,4,5,6,7,8,9",
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| H A D | other.json | 3 …re not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and…
4 "Counter": "0,1,2,3,4,5,6,7,8,9",
7 …re not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
22 …"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to a lock In Progr…
23 "Counter": "0,1,2,3,4,5,6,7",
26 …Counts the number of unhalted cycles a Core is blocked due to a lock In Progress issued by another…
32 …"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to an Accepted loc…
33 "Counter": "0,1,2,3,4,5,6,7",
36 …r of unhalted cycles a Core is blocked due to an Accepted lock it issued, includes both split and …
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| /linux/tools/perf/pmu-events/arch/x86/pantherlake/ |
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
23 "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
24 "Counter": "0,1,2,3,4,5,6,7",
33 "Counter": "0,1,2,3,4,5,6,7",
41 "BriefDescription": "Counts the number of BACLEARS due to a return branch.",
42 "Counter": "0,1,2,3,4,5,6,7",
50 "BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.",
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| H A D | virtual-memory.json | 3 …"BriefDescription": "Counts the number of page walks initiated by a demand load that missed the fi…
4 "Counter": "0,1,2,3,4,5,6,7",
12 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
13 "Counter": "0,1,2,3,4,5,6,7",
22 "Counter": "0,1,2,3,4,5,6,7,8,9",
31 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
32 "Counter": "0,1,2,3,4,5,6,7,8,9",
36 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
43 "Counter": "0,1,2,3,4,5,6,7",
52 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
[all …]
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| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7,8,9",
15 "Counter": "0,1,2,3,4,5,6,7,8,9",
25 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
26 "Counter": "0,1,2,3,4,5,6,7,8,9",
29 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
36 "Counter": "0,1,2,3,4,5,6,7,8,9",
45 "Counter": "0,1,2,3,4,5,6,7",
48 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
54 "Counter": "0,1,2,3,4,5,6,7,8,9",
63 "Counter": "0,1,2,3,4,5,6,7,8,9",
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| /linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 … evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) li…
13 "Counter": "0,1,2,3,4,5,6,7",
16 … of cache lines filled into the L2 cache that are in Exclusive state. Counts on a per core basis.",
22 "Counter": "0,1,2,3,4,5,6,7",
25 …er of cache lines filled into the L2 cache that are in Forward state. Counts on a per core basis.",
31 "Counter": "0,1,2,3,4,5,6,7",
34 …r of cache lines filled into the L2 cache that are in Modified state. Counts on a per core basis.",
40 "Counter": "0,1,2,3,4,5,6,7",
43 …ber of cache lines filled into the L2 cache that are in Shared state. Counts on a per core basis.",
[all …]
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| /linux/Documentation/i2c/ |
| H A D | i2c-sysfs.rst | 13 is a gap of knowledge to map from the I2C bus physical number and MUX topology
24 People who need to use Linux shell to interact with I2C subsystem on a system
40 There is a list of symbolic links under that directory. The links that
52 on bus 2 address 0x49 bound with a kernel driver.
73 For each physical I2C bus controller, the system vendor may assign a physical
80 Every I2C bus number you see in Linux I2C Sysfs is a logical I2C bus with a
84 Each logical I2C bus may be an abstraction of a physical I2C bus controller, or
85 an abstraction of a channel behind an I2C MUX. In case it is an abstraction of a
86 MUX channel, whenever we access an I2C device via a such logical bus, the kernel
93 If the logical I2C bus is a direct abstraction of a physical I2C bus controller,
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| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 … evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) li…
13 "Counter": "0,1,2,3,4,5,6,7",
16 … of cache lines filled into the L2 cache that are in Exclusive state. Counts on a per core basis.",
22 "Counter": "0,1,2,3,4,5,6,7",
25 …er of cache lines filled into the L2 cache that are in Forward state. Counts on a per core basis.",
31 "Counter": "0,1,2,3,4,5,6,7",
34 …r of cache lines filled into the L2 cache that are in Modified state. Counts on a per core basis.",
40 "Counter": "0,1,2,3,4,5,6,7",
43 …ber of cache lines filled into the L2 cache that are in Shared state. Counts on a per core basis.",
[all …]
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| /linux/scripts/gendwarfksyms/examples/ |
| H A D | kabi_ex.h | 42 int a; member
53 A, enumerator
65 * STABLE-NEXT: enumerator A = 0 ,
74 int a; member
81 * STABLE-NEXT: member base_type int byte_size(4) encoding(5) a data_member_location(0) ,
82 …r base_type [[ULONG:long unsigned int|unsigned long]] byte_size(8) encoding(7) data_member_locatio…
83 * STABLE-NEXT: member base_type [[ULONG]] byte_size(8) encoding(7) data_member_location(16)
88 int a; member
95 * STABLE-NEXT: member base_type int byte_size(4) encoding(5) a data_member_location(0) ,
96 * STABLE-NEXT: member base_type [[ULONG]] byte_size(8) encoding(7) data_member_location(8) ,
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| /linux/tools/perf/pmu-events/arch/x86/meteorlake/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
25 "Counter": "0,1,2,3,4,5,6,7",
34 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
35 "Counter": "0,1,2,3,4,5,6,7",
38 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
45 "Counter": "0,1,2,3,4,5,6,7",
49 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
55 "Counter": "0,1,2,3,4,5,6,7",
64 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
17 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
27 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
46 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
53 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
73 "Counter": "0,1,2,3,4,5,6,7",
84 …of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots…
85 "Counter": "0,1,2,3,4,5,6,7",
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| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
52 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
53 "Counter": "0,1,2,3,4,5,6,7",
56 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
62 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
52 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
53 "Counter": "0,1,2,3,4,5,6,7",
56 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
62 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
22 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
23 "Counter": "0,1,2,3,4,5,6,7",
26 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
32 "Counter": "0,1,2,3,4,5,6,7",
40 "Counter": "0,1,2,3,4,5,6,7",
49 "Counter": "0,1,2,3,4,5,6,7",
58 "Counter": "0,1,2,3,4,5,6,7",
67 "Counter": "0,1,2,3,4,5,6,7",
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|
| /linux/tools/perf/pmu-events/arch/x86/graniterapids/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
22 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
23 "Counter": "0,1,2,3,4,5,6,7",
26 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
32 "Counter": "0,1,2,3,4,5,6,7",
40 "Counter": "0,1,2,3,4,5,6,7",
49 "Counter": "0,1,2,3,4,5,6,7",
58 "Counter": "0,1,2,3,4,5,6,7",
67 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
22 "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
23 "Counter": "0,1,2,3,4,5,6,7",
26 "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
32 "Counter": "0,1,2,3,4,5,6,7",
40 "Counter": "0,1,2,3,4,5,6,7",
49 "Counter": "0,1,2,3,4,5,6,7",
58 "Counter": "0,1,2,3,4,5,6,7",
67 "Counter": "0,1,2,3,4,5,6,7",
70 { global() object
[all...] |