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/linux/lib/zlib_inflate/
H A Dinffixed.h1 /* inffixed.h -- table for decoding fixed codes
11 {96,7,0},{0,8,80},{0,8,16},{20,8,115},{18,7,31},{0,8,112},{0,8,48},
12 {0,9,192},{16,7,10},{0,8,96},{0,8,32},{0,9,160},{0,8,0},{0,8,128},
13 {0,8,64},{0,9,224},{16,7,6},{0,8,88},{0,8,24},{0,9,144},{19,7,59},
14 {0,8,120},{0,8,56},{0,9,208},{17,7,17},{0,8,104},{0,8,40},{0,9,176},
15 {0,8,8},{0,8,136},{0,8,72},{0,9,240},{16,7,4},{0,8,84},{0,8,20},
16 {21,8,227},{19,7,43},{0,8,116},{0,8,52},{0,9,200},{17,7,13},{0,8,100},
17 {0,8,36},{0,9,168},{0,8,4},{0,8,132},{0,8,68},{0,9,232},{16,7,8},
18 {0,8,92},{0,8,28},{0,9,152},{20,7,83},{0,8,124},{0,8,60},{0,9,216},
19 {18,7,23},{0,8,108},{0,8,44},{0,9,184},{0,8,12},{0,8,140},{0,8,76},
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_qp_tables.c1 // SPDX-License-Identifier: MIT
65 { 9, 9, 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5,
67 { 14, 14, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10, 9, 9, 9, 8, 8,
68 8, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3 }
76 { 8, 7, 7, 6, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 2, 2, 1, 1, 1, 1, 1,
78 { 8, 8, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 4, 3, 3, 2, 2, 2, 2, 2,
80 { 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 4, 4, 3, 2, 2, 2, 2, 2,
82 { 9, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 5, 4, 4, 3, 3, 3, 3, 3,
84 { 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 4, 4, 3, 3, 3, 3, 3,
86 { 10, 10, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 6, 5, 5, 4, 4, 4, 4, 3,
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2042.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
8 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
9 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/reset/sophgo,sg2042-reset.h>
13 #include "sg2042-cpus.dtsi"
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
/linux/drivers/staging/media/ipu3/
H A Dipu3-tables.c1 // SPDX-License-Identifier: GPL-2.0
4 #include "ipu3-tables.h"
24 .even = { { 0, 3, 122, 7, 3, 0, 0 },
25 { 0, 0, 122, 7, 7, -1, 0 },
26 { 0, -3, 122, 7, 10, -1, 0 },
27 { 0, -5, 121, 7, 14, -2, 0 },
28 { 0, -7, 120, 7, 18, -3, 0 },
29 { 0, -9, 118, 7, 23, -4, 0 },
30 { 0, -11, 116, 7, 27, -4, 0 },
31 { 0, -12, 113, 7, 32, -5, 0 },
[all …]
/linux/arch/powerpc/crypto/
H A Dcurve25519-ppc64le_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 # [1] https://github.com/dot-asm/cryptogams/
11 # Copyright (c) 2006-2017, CRYPTOGAMS by <appro@openssl.org>
58 # - Added x25519_fe51_sqr_times, x25519_fe51_frombytes, x25519_fe51_tobytes
61 # Copyright 2024- IBM Corp.
63 # X25519 lower-level primitives for PPC64.
73 stdu 1,-144(1)
87 ld 7,0(4)
89 ld 9,16(4)
93 mulld 22,7,6
[all …]
H A Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
17 # 4. c += d; b ^= c; b <<<= 7
22 # row3 = (row3 + row4), row2 = row3 xor row2, row2 rotate each word by 7
43 #include <asm/asm-offsets.h>
44 #include <asm/asm-compat.h>
81 stdu 1,-752(1)
102 addi 9, 1, 256
103 SAVE_VRS 20, 0, 9
104 SAVE_VRS 21, 16, 9
[all …]
H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
26 # to 9 vectors for multiplications.
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
[all …]
H A Daes-tab-4k.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 * For the safety-conscious it has to be noted that they might be vulnerable
32 /* encryption table, same as crypto_ft_tab in crypto/aes-generic.c */
33 .long R(c6, 63, 63, a5), R(f8, 7c, 7c, 84)
34 .long R(ee, 77, 77, 99), R(f6, 7b, 7b, 8d)
38 .long R(ce, 67, 67, a9), R(56, 2b, 2b, 7d)
40 .long R(4d, ab, ab, e6), R(ec, 76, 76, 9a)
41 .long R(8f, ca, ca, 45), R(1f, 82, 82, 9d)
42 .long R(89, c9, c9, 40), R(fa, 7d, 7d, 87)
47 .long R(23, 9c, 9c, bf), R(53, a4, a4, f7)
[all …]
/linux/include/dt-bindings/memory/
H A Dmt8186-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
22 * modules dma-address-region larbs-ports
24 * vcodec 4G ~ 8G larb4/7
27 * CCU0 0x24000_0000 ~ 0x243ff_ffff larb13: port 9/10
32 /* LARB 0 -- MMSYS */
38 /* LARB 1 -- MMSYS */
45 /* LARB 2 -- MMSYS */
52 /* LARB 4 -- VDEC */
60 #define IOMMU_PORT_L4_HW_VDEC_VLD_EXT MTK_M4U_ID(4, 7)
[all …]
H A Dmt8192-larb-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
18 * modules dma-address-region larbs-ports
20 * vcodec 4G ~ 8G larb4/5/7
21 * cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20
22 * CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10
44 #define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_ID(1, 7)
63 #define M4U_PORT_L4_VDEC_VLD_EXT MTK_M4U_ID(4, 7)
65 #define M4U_PORT_L4_VDEC_AVC_MV_EXT MTK_M4U_ID(4, 9)
76 #define M4U_PORT_L5_VDEC_UFO_ENC_EXT MTK_M4U_ID(5, 7)
[all …]
H A Dmt8195-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/memory/mtk-memory-port.h>
20 * modules dma-address-region larbs-ports
29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
30 * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
81 #define M4U_PORT_L5_FAKE MTK_M4U_ID(5, 7)
90 #define M4U_PORT_L7_IMG_WPE_RDMA0 MTK_M4U_ID(7, 0)
91 #define M4U_PORT_L7_IMG_WPE_RDMA1 MTK_M4U_ID(7, 1)
92 #define M4U_PORT_L7_IMG_WPE_WDMA0 MTK_M4U_ID(7, 2)
100 #define M4U_PORT_L9_IMG_IMGI_T1_A MTK_M4U_ID(9, 0)
[all …]
/linux/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c1 // SPDX-License-Identifier: MIT
35 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
49 pps_header->HB1 = DP_SDP_PPS; in drm_dsc_dp_pps_header_init()
50 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; in drm_dsc_dp_pps_header_init()
55 * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
57 * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
82 * drm_dsc_pps_payload_pack() - Populates the DSC PPS
110 pps_payload->dsc_version = in drm_dsc_pps_payload_pack()
111 dsc_cfg->dsc_version_minor | in drm_dsc_pps_payload_pack()
112 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; in drm_dsc_pps_payload_pack()
[all …]
/linux/drivers/clk/rockchip/
H A Drst-rk3576.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
29 RK3576_CRU_RESET_OFFSET(SRST_A_SECURE_HIGH_BIU, 1, 7),
40 RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
41 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3),
42 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_1, 7, 4),
43 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_0, 7, 5),
44 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_1, 7, 6),
45 RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_0, 7, 7),
46 RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_1, 7, 8),
[all …]
H A Drst-rk3588.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
31 RK3588_CRU_RESET_OFFSET(SRST_CSIPHY0, 1, 7), // missing in TRM
33 RK3588_CRU_RESET_OFFSET(SRST_CSIPHY1, 1, 9), // missing in TRM
42 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_CMN, 2, 9),
61 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO3_5, 4, 7),
63 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_EMMCIO, 4, 9),
69 RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2VO1USB, 5, 7),
79 RK3588_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
80 RK3588_CRU_RESET_OFFSET(SRST_P_AUDIO_BIU, 7, 3),
[all …]
/linux/drivers/pinctrl/sunplus/
H A Dsppctl_sp7021.c1 // SPDX-License-Identifier: GPL-2.0
19 D_PIS(0, 4), D_PIS(0, 5), D_PIS(0, 6), D_PIS(0, 7),
21 D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7),
23 D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7),
25 D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7),
27 D_PIS(4, 4), D_PIS(4, 5), D_PIS(4, 6), D_PIS(4, 7),
29 D_PIS(5, 4), D_PIS(5, 5), D_PIS(5, 6), D_PIS(5, 7),
31 D_PIS(6, 4), D_PIS(6, 5), D_PIS(6, 6), D_PIS(6, 7),
32 D_PIS(7, 0), D_PIS(7, 1), D_PIS(7, 2), D_PIS(7, 3),
33 D_PIS(7, 4), D_PIS(7, 5), D_PIS(7, 6), D_PIS(7, 7),
[all …]
/linux/drivers/media/pci/cobalt/
H A Dcobalt-cpld.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
11 #include "cobalt-cpld.h"
17 return cobalt_bus_read32(cobalt->bar1, ADRS(offset)); in cpld_read()
22 return cobalt_bus_write32(cobalt->bar1, ADRS(offset), val); in cpld_write()
36 …cobalt_info("CPLD HSMA Clk Osc register (read/write) - Must set wr trigger to load default values\… in cpld_info_ver3()
37 cobalt_info("\t\tRegister #7:\t0x%04x (0x0022)\n", in cpld_info_ver3()
41 cobalt_info("\t\tRegister #9:\t0x%04x (0x00fa)\n", in cpld_info_ver3()
133 { 7, 7, 1 }, { 8, 4, 2 }, { 9, 9, 1 },
135 { 14, 7, 2 }, { 16, 4, 4 }, { 18, 9, 2 },
[all …]
/linux/drivers/pinctrl/stm32/
H A Dpinctrl-stm32mp257.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
10 #include "pinctrl-stm32.h"
22 STM32_FUNCTION(7, "USART3_TX"),
24 STM32_FUNCTION(9, "TIM5_CH2"),
38 STM32_FUNCTION(7, "USART6_CK"),
40 STM32_FUNCTION(9, "I2C4_SDA"),
55 STM32_FUNCTION(7, "USART1_RX"),
56 STM32_FUNCTION(9, "I3C1_SDA"),
71 STM32_FUNCTION(7, "USART1_TX"),
[all …]
/linux/lib/crypto/
H A Dblake2s-generic.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
20 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
21 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
22 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
23 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
24 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
25 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
26 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
27 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
[all …]
/linux/drivers/staging/media/rkvdec/
H A Drkvdec-h264.c1 // SPDX-License-Identifier: GPL-2.0
9 * Jeffy Chen <jeffy.chen@rock-chips.com>
12 #include <media/v4l2-h264.h>
13 #include <media/v4l2-mem2mem.h>
16 #include "rkvdec-regs.h"
55 #define PIC_WIDTH_IN_MBS PS_FIELD(38, 9)
56 #define PIC_HEIGHT_IN_MBS PS_FIELD(47, 9)
74 #define PIC_INIT_QP_MINUS26 PS_FIELD(156, 7)
86 #define DPB_OFFS(i, j) (288 + ((j) * 32 * 7) + ((i) * 7))
133 /* Table 9-12 – Values of variables m and n for ctxIdx from 0 to 10 */
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8192.c1 // SPDX-License-Identifier: GPL-2.0
9 #include "pinctrl-mtk-mt8192.h"
10 #include "pinctrl-paris.h"
50 PIN_FIELD_BASE(5, 5, 4, 0x00f0, 0x10, 9, 1),
51 PIN_FIELD_BASE(6, 6, 4, 0x00f0, 0x10, 9, 1),
52 PIN_FIELD_BASE(7, 7, 4, 0x00f0, 0x10, 9, 1),
53 PIN_FIELD_BASE(8, 8, 4, 0x00f0, 0x10, 9, 1),
54 PIN_FIELD_BASE(9, 9, 4, 0x00f0, 0x10, 5, 1),
63 PIN_FIELD_BASE(18, 18, 7, 0x0100, 0x10, 4, 1),
64 PIN_FIELD_BASE(19, 19, 7, 0x0100, 0x10, 4, 1),
[all …]
/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-cp110.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include "pinctrl-mvebu.h"
24 * - In Armada7K (single CP) almost all the MPPs are available (except the
26 * - In Armada8K (dual CP) the MPPs are split into 2 parts, MPPs 0-31 from
27 * CPS, and MPPs 32-62 from CPM, the below flags (V_ARMADA_8K_CPM,
48 MPP_FUNCTION(7, "mss_i2c", "sda"),
50 MPP_FUNCTION(9, "sata0", "present_act"),
59 MPP_FUNCTION(7, "mss_i2c", "sck"),
61 MPP_FUNCTION(9, "sata1", "present_act"),
71 MPP_FUNCTION(7, "i2c1", "sck"),
[all …]
/linux/arch/arm/mach-omap1/
H A Dmux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/arch/arm/mach-omap1/mux.c
7 * Copyright (C) 2003 - 2008 Nokia Corporation
15 #include <linux/soc/ti/omap1-io.h>
30 MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
31 MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
44 MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
53 MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
54 MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)
59 MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1)
[all …]
/linux/crypto/
H A Dblake2b_generic.c1 // SPDX-License-Identifier: (GPL-2.0-only OR Apache-2.0)
11 * - CC0 1.0 Universal : http://creativecommons.org/publicdomain/zero/1.0
12 * - OpenSSL license : https://www.openssl.org/source/license.html
13 * - Apache 2.0 : https://www.apache.org/licenses/LICENSE-2.0
26 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
27 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
28 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
29 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
30 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
31 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
[all …]
/linux/arch/x86/crypto/
H A Dblake2s-core.S1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
3 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
4 * Copyright (C) 2017-2019 Samuel Neves <sneves@dei.uc.pt>. All Rights Reserved.
22 .byte 0, 2, 4, 6, 1, 3, 5, 7, 14, 8, 10, 12, 15, 9, 11, 13
23 .byte 14, 4, 9, 13, 10, 8, 15, 6, 5, 1, 0, 11, 3, 12, 2, 7
24 .byte 11, 12, 5, 15, 8, 0, 2, 13, 9, 10, 3, 7, 4, 14, 6, 1
25 .byte 7, 3, 13, 11, 9, 1, 12, 14, 15, 2, 5, 4, 8, 6, 10, 0
26 .byte 9, 5, 2, 10, 0, 7, 4, 15, 3, 14, 11, 6, 13, 1, 12, 8
27 .byte 2, 6, 0, 8, 12, 10, 11, 3, 1, 4, 7, 15, 9, 13, 5, 14
28 .byte 12, 1, 14, 4, 5, 15, 13, 10, 8, 0, 6, 9, 11, 7, 3, 2
[all …]
/linux/Documentation/translations/zh_CN/core-api/
H A Dpacking.rst1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
54 以下示例介绍了打包u64字段的内存布局。打包缓冲区中的字节偏移量始终默认为0，1...7。
62 7 6 5 4
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
[all …]

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