Lines Matching +full:7 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
31 RK3588_CRU_RESET_OFFSET(SRST_CSIPHY0, 1, 7), // missing in TRM
33 RK3588_CRU_RESET_OFFSET(SRST_CSIPHY1, 1, 9), // missing in TRM
42 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_CMN, 2, 9),
61 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO3_5, 4, 7),
63 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_EMMCIO, 4, 9),
69 RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2VO1USB, 5, 7),
79 RK3588_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
80 RK3588_CRU_RESET_OFFSET(SRST_P_AUDIO_BIU, 7, 3),
81 RK3588_CRU_RESET_OFFSET(SRST_H_I2S0_8CH, 7, 4),
82 RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_TX, 7, 7),
83 RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_RX, 7, 10),
84 RK3588_CRU_RESET_OFFSET(SRST_P_ACDCDIG, 7, 11),
85 RK3588_CRU_RESET_OFFSET(SRST_H_I2S2_2CH, 7, 12),
86 RK3588_CRU_RESET_OFFSET(SRST_H_I2S3_2CH, 7, 13),
95 RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF0, 9, 1),
96 RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF1, 9, 2),
97 RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF1, 9, 5),
98 RK3588_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 6),
99 RK3588_CRU_RESET_OFFSET(SRST_PDM1, 9, 7),
108 RK3588_CRU_RESET_OFFSET(SRST_A_DMAC2, 10, 7),
110 RK3588_CRU_RESET_OFFSET(SRST_P_I2C2, 10, 9),
126 RK3588_CRU_RESET_OFFSET(SRST_I2C8, 11, 7),
128 RK3588_CRU_RESET_OFFSET(SRST_CAN0, 11, 9),
143 RK3588_CRU_RESET_OFFSET(SRST_P_UART6, 12, 7),
145 RK3588_CRU_RESET_OFFSET(SRST_P_UART8, 12, 9),
153 RK3588_CRU_RESET_OFFSET(SRST_S_UART5, 13, 9),
161 RK3588_CRU_RESET_OFFSET(SRST_P_SPI1, 14, 7),
163 RK3588_CRU_RESET_OFFSET(SRST_P_SPI3, 14, 9),
178 RK3588_CRU_RESET_OFFSET(SRST_PWM2, 15, 7),
179 RK3588_CRU_RESET_OFFSET(SRST_P_PWM3, 15, 9),
193 RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER8, 16, 7),
195 RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER10, 16, 9),
211 RK3588_CRU_RESET_OFFSET(SRST_P_DECOM, 17, 7),
213 RK3588_CRU_RESET_OFFSET(SRST_P_TOP, 17, 9),
228 RK3588_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 18, 9),
245 RK3588_CRU_RESET_OFFSET(SRST_SBR_CH0, 20, 7),
247 RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH0, 20, 9),
263 RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH1, 21, 7),
277 RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 22, 7),
288 RK3588_CRU_RESET_OFFSET(SRST_SBR_CH2, 23, 7),
290 RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH2, 23, 9),
306 RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH3, 24, 7),
320 RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH2, 25, 7),
346 RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER1, 29, 9),
359 RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 30, 7),
361 RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0_BIU, 30, 9),
369 RK3588_CRU_RESET_OFFSET(SRST_B_EMMC, 31, 7),
371 RK3588_CRU_RESET_OFFSET(SRST_S_SFC, 31, 9),
380 RK3588_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 32, 9),
399 RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PCIE, 34, 7),
401 RK3588_CRU_RESET_OFFSET(SRST_A_MMU_BIU, 34, 9),
404 RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG2, 35, 7),
410 RK3588_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 7),
412 RK3588_CRU_RESET_OFFSET(SRST_A_SATA2, 37, 9),
426 RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CA, 40, 7),
428 RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CORE, 40, 9),
436 RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_HEVC_CA, 41, 7),
443 RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 42, 7),
460 RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER_BIU, 44, 7),
462 RK3588_CRU_RESET_OFFSET(SRST_H_VPU, 44, 9),
478 RK3588_CRU_RESET_OFFSET(SRST_H_RGA2, 45, 7),
480 RK3588_CRU_RESET_OFFSET(SRST_RGA2_CORE, 45, 9),
504 RK3588_CRU_RESET_OFFSET(SRST_A_VICAP, 49, 7),
515 RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 50, 7),
517 RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_5, 50, 9),
523 RK3588_CRU_RESET_OFFSET(SRST_CSIHOST3_VICAP, 51, 7),
525 RK3588_CRU_RESET_OFFSET(SRST_CSIHOST5_VICAP, 51, 9),
532 RK3588_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 52, 7),
534 RK3588_CRU_RESET_OFFSET(SRST_A_VOP, 52, 9),
547 RK3588_CRU_RESET_OFFSET(SRST_DSIHOST1, 53, 7),
549 RK3588_CRU_RESET_OFFSET(SRST_P_VOP_CHANNEL_BIU, 53, 9),
554 RK3588_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 55, 7),
556 RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 55, 9),
566 RK3588_CRU_RESET_OFFSET(SRST_DP1, 56, 9),
575 RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF5_DP1, 57, 7),
580 RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX_BIU, 59, 7),
582 RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9),
601 RK3588_CRU_RESET_OFFSET(SRST_HDMITX1_REF, 61, 7),
602 RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX, 61, 9),
619 RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF3, 63, 7),
639 RK3588_CRU_RESET_OFFSET(SRST_M_I2S10_8CH_RX, 65, 7),
646 RK3588_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 66, 9),
669 RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 69, 7),
683 RK3588_CRU_RESET_OFFSET(SRST_P_WDT, 70, 7),
685 RK3588_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 70, 9),
697 RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_BOT_RIGHT, 72, 7),
699 RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_1_GRF0, 72, 9),
715 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1, 73, 7), // missing in TRM
717 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_ROPLL, 73, 9), // missing in TRM
740 RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY1, 77, 7),
750 RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY2, 0, 7),
752 RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 9),
768 RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 1, 7),
780 RK3588_PMU1CRU_RESET_OFFSET(SRST_H_I2S1_8CH, 2, 7),
800 RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_0, 4, 7),
802 RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_0, 4, 9),
824 RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_CORE, 1, 9),