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/linux/Documentation/ABI/stable/
H A Dsysfs-class-tpm97 PCR-00: 3A 3F 78 0F 11 A4 B4 99 69 FC AA 80 CD 6E 39 57 C3 3B 22 75
98 PCR-01: 3A 3F 78 0F 11 A4 B4 99 69 FC AA 80 CD 6E 39 57 C3 3B 22 75
99 PCR-02: 3A 3F 78 0F 11 A4 B4 99 69 FC AA 80 CD 6E 39 57 C3 3B 22 75
100 PCR-03: 3A 3F 78 0F 11 A4 B4 99 69 FC AA 80 CD 6E 39 57 C3 3B 22 75
101 PCR-04: 3A 3F 78 0F 11 A4 B4 99 69 FC AA 80 CD 6E 39 57 C3 3B 22 75
137 1E 30 38 6C 70 63 69 AB E2 50 DF 49 05 2E E1 8D
138 6F 78 44 DA 57 43 69 EE 76 6C 38 8A E9 8E A3 F0
/linux/drivers/staging/media/ipu3/
H A Dipu3-tables.c167 { 0, -14, 86, 7, 69, -13, 0 },
169 { 0, -13, 69, 7, 86, -14, 0 },
200 { 0, -14, 86, 7, 69, -13, 0 },
202 { 0, -13, 69, 7, 86, -14, 0 },
238 { 0, -13, 69, 7, 86, -14, 0 },
258 { 0, -14, 86, 7, 69, -13, 0 },
303 { 0, -13, 69, 7, 86, -14, 0 },
323 { 0, -14, 86, 7, 69, -13, 0 },
379 { 0, -13, 85, 7, 69, -13, 0 },
380 { 0, -13, 69, 7, 85, -13, 0 },
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt7629.c36 PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1),
46 PIN_FIELD(51, 69, 0x6100, 0x10, 0, 1),
56 PIN_FIELD(51, 69, 0x6400, 0x10, 0, 1),
66 PIN_FIELD(51, 69, 0x6500, 0x10, 0, 1),
76 PIN_FIELD(51, 69, 0x6600, 0x10, 0, 4),
86 PIN_FIELD(51, 69, 0x6200, 0x10, 0, 4),
96 PIN_FIELD(51, 69, 0x6300, 0x10, 0, 4),
184 MT7629_PIN(69, "UART0_RXD", 69),
274 static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, };
H A Dpinctrl-mt8167.c109 MTK_PIN_DRV_GRP(69, 0xd50, 0, 2),
163 MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4),
211 MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1),
260 MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1),
H A Dpinctrl-mt8516.c109 MTK_PIN_DRV_GRP(69, 0xd50, 0, 2),
163 MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4),
211 MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1),
260 MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1),
H A Dpinctrl-mt7986.c127 PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1),
181 PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
200 PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
219 PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x40, 0x10, 1, 1),
277 PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
445 MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
549 MT7986_PIN(69, "WF0_DIG_RESETB"),
653 MT7986_PIN(69, "WF0_DIG_RESETB"),
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dinitvals_phy.h206 { 69, 0x12 },
213 { 69, 0x15 },
222 { 69, 0x12 },
232 { 69, 0x15 },
247 { 69, 0x12 },
254 { 69, 0x15 },
/linux/drivers/gpu/drm/omapdrm/dss/
H A Ddispc_coefs.c115 { 0, 5, 69, 54, 0 },
117 { 0, 54, 69, 5, 0 },
126 { 0, 5, 69, 54, 0 },
128 { 0, 54, 69, 5, 0 },
213 { 0, 45, 69, 16, -2 },
217 { -2, 16, 69, 45, 0 },
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddispc_coefs.c117 { 0, 5, 69, 54, 0 },
119 { 0, 54, 69, 5, 0 },
128 { 0, 5, 69, 54, 0 },
130 { 0, 54, 69, 5, 0 },
215 { 0, 45, 69, 16, -2 },
219 { -2, 16, 69, 45, 0 },
/linux/arch/powerpc/include/asm/book3s/64/
H A Dkup.h48 BEGIN_MMU_FTR_SECTION_NESTED(69)
52 END_MMU_FTR_SECTION_NESTED_IFCLR(MMU_FTR_BOOK3S_KUEP, 69)
159 BEGIN_MMU_FTR_SECTION_NESTED(69)
169 END_MMU_FTR_SECTION_NESTED_IFSET(MMU_FTR_KUAP, 69)
/linux/drivers/clk/rockchip/
H A Drst-rk3576.c517 RK3576_CRU_RESET_OFFSET(SRST_GPU, 69, 3),
518 RK3576_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 69, 6),
519 RK3576_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 69, 7),
520 RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9),
521 RK3576_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 69, 13),
522 RK3576_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 69, 14),
523 RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_GPU, 69, 15),
H A Drst-rk3588.c666 RK3588_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 69, 4),
667 RK3588_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 69, 5),
668 RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 69, 6),
669 RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 69, 7),
670 RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S200_BIU, 69, 10),
671 RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S400_BIU, 69, 11),
672 RK3588_CRU_RESET_OFFSET(SRST_H_AHB2APB, 69, 12),
673 RK3588_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 69, 13),
674 RK3588_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 69, 14),
/linux/tools/memory-model/scripts/
H A Dinitlitmushist.sh26 # 9 15m57.80s 105m58.101s 69 5156
27 # 10 16m14.13s 103m35.009s 69 5165
/linux/include/dt-bindings/clock/
H A Dgoogle,gs101.h83 #define CLK_MOUT_CMU_PERIC1_IP 69
312 #define CLK_APM_PLL_DIV2_APM 69
501 #define CLK_GOUT_MISC_SYSREG_MISC_PCLK 69
577 #define CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK 69
H A Drk3036-cru.h20 #define SCLK_SDIO 69
151 #define SRST_USBOTG0 69
H A Dqcom,gcc-ipq4019.h88 #define GCC_FEPLL125DLY_CLK 69
165 #define GCC_QDSS_BCR 69
H A Dexynos5433.h265 #define CLK_DIV_SCLK_DECON_TV_VCLK 69
566 #define CLK_ACLK_BTS_PCIE 69
709 #define CLK_PCLK_SMMU_DECON1X 69
1106 #define CLK_PCLK_SCALERC 69
1186 #define CLK_ACLK_ASYNCAPBM_LITE_A 69
1324 #define CLK_ACLK_AXIUS_LITE_C 69
/linux/Documentation/devicetree/bindings/thermal/
H A Drcar-thermal.yaml115 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
131 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8516-pinfunc.h429 #define MT8516_PIN_69_MSDC2_CLK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
430 #define MT8516_PIN_69_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(69) | 1)
431 #define MT8516_PIN_69_MSDC2_CLK__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(69) | 2)
432 #define MT8516_PIN_69_MSDC2_CLK__FUNC_SCL1_0 (MTK_PIN_NO(69) | 3)
433 #define MT8516_PIN_69_MSDC2_CLK__FUNC_USB_SCL (MTK_PIN_NO(69) | 5)
434 #define MT8516_PIN_69_MSDC2_CLK__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 6)
435 #define MT8516_PIN_69_MSDC2_CLK__FUNC_DBG_MON_B_16 (MTK_PIN_NO(69) | 7)
H A Dmt8173-pinfunc.h335 #define MT8173_PIN_69_SPI_CK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
336 #define MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_ (MTK_PIN_NO(69) | 1)
337 #define MT8173_PIN_69_SPI_CK__FUNC_I2S3_DO_1 (MTK_PIN_NO(69) | 2)
338 #define MT8173_PIN_69_SPI_CK__FUNC_PWM0 (MTK_PIN_NO(69) | 3)
339 #define MT8173_PIN_69_SPI_CK__FUNC_PWM5 (MTK_PIN_NO(69) | 4)
340 #define MT8173_PIN_69_SPI_CK__FUNC_I2S2_MCK (MTK_PIN_NO(69) | 5)
341 #define MT8173_PIN_69_SPI_CK__FUNC_DBG_MON_B_19_ (MTK_PIN_NO(69) | 7)
H A Dmt8167-pinfunc.h480 #define MT8167_PIN_69_MSDC2_CLK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
481 #define MT8167_PIN_69_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(69) | 1)
482 #define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(69) | 2)
483 #define MT8167_PIN_69_MSDC2_CLK__FUNC_SCL1_0 (MTK_PIN_NO(69) | 3)
484 #define MT8167_PIN_69_MSDC2_CLK__FUNC_DPI_D21 (MTK_PIN_NO(69) | 4)
485 #define MT8167_PIN_69_MSDC2_CLK__FUNC_USB_SCL (MTK_PIN_NO(69) | 5)
486 #define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 6)
487 #define MT8167_PIN_69_MSDC2_CLK__FUNC_DBG_MON_B_16 (MTK_PIN_NO(69) | 7)
/linux/drivers/s390/char/
H A Ddefkeymap.map74 keycode 69 = aacute E
150 shift control keycode 69 = F17
/linux/include/dt-bindings/sound/
H A Dqcom,q6dsp-lpass-ports.h74 #define TERTIARY_TDM_TX_6 69
220 #define LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK 69
/linux/arch/powerpc/crypto/
H A Daes-tab-4k.S63 .long R(cd, eb, eb, 26), R(4e, 27, 27, 69)
142 .long R(ae, 57, 57, f9), R(69, b9, b9, d0)
147 .long R(d2, 69, 69, bb), R(a9, d9, d9, 70)
179 .long R(49, e0, 69, 29), R(8e, c9, c8, 44)
197 .long R(f3, 07, f2, f0), R(4e, 69, e2, a1)
223 .long R(5a, 77, 4b, 69), R(1c, 12, 1a, 16)
252 .long R(9f, 5d, 80, be), R(69, d0, 93, 7c)
/linux/drivers/pinctrl/intel/
H A Dpinctrl-broxton.c98 PINCTRL_PIN(69, "GP_CAMERASB07"),
252 PINCTRL_PIN(69, "GP_SSP_2_FS2"),
261 static const unsigned int bxt_northwest_ssp2_pins[] = { 66, 67, 68, 69, 70, 71 };
262 static const unsigned int bxt_northwest_uart3_pins[] = { 67, 68, 69, 70 };
597 PINCTRL_PIN(69, "CX_PRDY_B"),
730 PINCTRL_PIN(69, "GP_SSP_1_RXD"),
741 static const unsigned int apl_northwest_ssp1_pins[] = { 66, 67, 68, 69, 70 };
743 static const unsigned int apl_northwest_uart3_pins[] = { 67, 68, 69, 70 };

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