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/linux/include/linux/
H A Dmath64.h10 #if BITS_PER_LONG == 64
16 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
17 * @dividend: unsigned 64bit dividend
18 * @divisor: unsigned 32bit divisor
19 * @remainder: pointer to unsigned 32bit remainder
23 * This is commonly provided by 32bit archs to provide an optimized 64bit
33 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
34 * @dividend: signed 64bit dividend
35 * @divisor: signed 32bit divisor
36 * @remainder: pointer to signed 32bit remainder
[all …]
H A Dexportfs.h34 * 32bit inode number, 32 bit generation number.
39 * 32bit inode number, 32 bit generation number,
40 * 32 bit parent directory inode number.
45 * 64 bit object ID, 64 bit root object ID,
46 * 32 bit generation number.
51 * 64 bit object ID, 64 bit root object ID,
52 * 32 bit generation number,
53 * 64 bit parent object ID, 32 bit parent generation.
58 * 64 bit object ID, 64 bit root object ID,
59 * 32 bit generation number,
[all …]
/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNQGAMA 64G 3.3V 8-bit",
50 {"SDTNRGAMA 64G 3.3V 8-bit",
53 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
[all …]
/linux/arch/x86/crypto/
H A DKconfig17 Architecture: x86 (32-bit and 64-bit) using:
21 Some algorithm implementations are supported only in 64-bit builds,
26 depends on 64BIT
38 depends on 64BIT
49 depends on 64BIT
62 depends on 64BIT
73 depends on 64BIT
89 depends on 64BIT
106 depends on 64BIT
120 depends on 64BIT
[all …]
/linux/arch/parisc/
H A DKconfig5 select ARCH_32BIT_OFF_T if !64BIT
20 select ARCH_SPLIT_ARG64 if !64BIT
43 select GENERIC_ATOMIC64 if !64BIT
93 select HAVE_FUNCTION_DESCRIPTORS if 64BIT
127 select GENERIC_BUG_RELATIVE_POINTERS if 64BIT
146 default 18 if 64BIT
153 default 18 if 64BIT
180 default 3 if 64BIT && PARISC_PAGE_SIZE_4KB
194 that can run on all 32-bit PA CPUs (albeit not optimally fast),
197 Specifying "PA8000" here will allow you to select a 64-bit kernel
[all …]
/linux/drivers/gpio/
H A Dgpio-xilinx.c31 #define XGPIO_GIER_IE BIT(31)
62 DECLARE_BITMAP(map, 64);
63 DECLARE_BITMAP(state, 64);
64 DECLARE_BITMAP(last_irq_read, 64);
65 DECLARE_BITMAP(dir, 64);
68 DECLARE_BITMAP(enable, 64);
69 DECLARE_BITMAP(rising_edge, 64);
70 DECLARE_BITMAP(falling_edge, 64);
86 static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) in xgpio_read_ch() argument
88 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); in xgpio_read_ch()
[all …]
/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn23xx_pf_regs.h74 /* 2 scatch registers (64-bit) */
80 /* 1 registers (64-bit) - SLI_CTL_STATUS */
83 /* SLI Packet Input Jabber Register (64 bit register)
117 /* 4 registers (64-bit) for mapping IOQs to MACs(PEMs)-
122 /*1 register (64-bit) to determine whether IOQs are in reset. */
141 /* Starting bit of the TRS field in CN23XX_SLI_PKT_MAC_RINFO64 register */
143 /* Starting bit of SRN field in CN23XX_SLI_PKT_MAC_RINFO64 register */
145 /* Starting bit of RPVF field in CN23XX_SLI_PKT_MAC_RINFO64 register */
147 /* Starting bit of NVFS field in CN23XX_SLI_PKT_MAC_RINFO64 register */
152 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
[all …]
H A Dcn23xx_vf_regs.h52 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
55 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
58 /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
61 /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
64 /* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data &
87 #define CN23XX_PKT_INPUT_CTL_MAC_NUM BIT(29)
92 #define CN23XX_PKT_INPUT_CTL_IS_64B BIT(24)
93 #define CN23XX_PKT_INPUT_CTL_RST BIT(23)
94 #define CN23XX_PKT_INPUT_CTL_QUIET BIT(28)
95 #define CN23XX_PKT_INPUT_CTL_RING_ENB BIT(22)
[all …]
H A Dcn66xx_regs.h89 /* 1 register (32-bit) to enable Input queues */
92 /* 1 register (32-bit) to enable Output queues */
95 /* 1 register (32-bit) to determine whether Output queues are in reset. */
98 /* 1 register (32-bit) to determine whether Input queues are in reset. */
103 /* 1 register (32-bit) - instr. size of each input queue. */
121 /* 1 register (64-bit) - Back Pressure for each input queue - SLI_PKT0_IN_BP */
127 /* 1 register (32-bit) - ES, RO, NS, Arbitration for Input Queue Data &
132 /* 1 register (64-bit) - Number of instructions to read at one time
137 /* 1 register (64-bit) - Assign Input ring to MAC port
162 #define CN6XXX_INPUT_CTL_ROUND_ROBIN_ARB BIT(22)
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dtg3.h21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
285 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
286 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
307 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
308 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
309 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
310 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
311 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
[all …]
/linux/drivers/acpi/acpica/
H A Dtbfadt.c166 * Bit width field in the GAS is only one byte long, 255 max. in acpi_tb_init_generic_address()
178 "%s - 32-bit FADT register is too long (%u bytes, %u bits) " in acpi_tb_init_generic_address()
188 * The 64-bit Address field is non-aligned in the byte packed in acpi_tb_init_generic_address()
206 * address32 - 32-bit address of the register
207 * address64 - 64-bit address of the register
209 * RETURN: The resolved 64-bit address
211 * DESCRIPTION: Select between 32-bit and 64-bit versions of addresses within
217 * the 32-bit and 64-bit address fields (FIRMWARE_CTRL/X_FIRMWARE_CTRL and
222 * By default, as per the ACPICA specification, a valid 64-bit address is
223 * used regardless of the value of the 32-bit address. However, this
[all …]
H A Dtbutils.c146 * table_entry_size - sizeof 32 or 64 (RSDT or XSDT)
150 * DESCRIPTION: Get one root table entry. Handles 32-bit and 64-bit cases on
151 * both 32-bit and 64-bit platforms
153 * NOTE: acpi_physical_address is 32-bit on 32-bit platforms, 64-bit on
154 * 64-bit platforms.
165 * Get the table physical address (32-bit for RSDT, 64-bit for XSDT): in acpi_tb_get_root_table_entry()
166 * Note: Addresses are 32-bit aligned (not 64) in both RSDT and XSDT in acpi_tb_get_root_table_entry()
170 * 32-bit platform, RSDT: Return 32-bit table entry in acpi_tb_get_root_table_entry()
171 * 64-bit platform, RSDT: Expand 32-bit to 64-bit and return in acpi_tb_get_root_table_entry()
177 * 32-bit platform, XSDT: Truncate 64-bit to 32-bit and return in acpi_tb_get_root_table_entry()
[all …]
/linux/lib/math/
H A Ddiv64.c10 * Generic C version of 64bit/32bit division and modulo, with
11 * 64bit result and 32bit remainder.
28 /* Not needed on 64bit architectures */
39 /* Reduce the thing a bit first */ in __div64_32()
88 * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
89 * @dividend: 64bit dividend
90 * @divisor: 64bit divisor
91 * @remainder: 64bit remainder
95 * is kept distinct to avoid slowing down the div64_u64 operation on 32bit
128 * div64_u64 - unsigned 64bit divide with 64bit divisor
[all …]
/linux/drivers/net/can/flexcan/
H A Dflexcan.h25 * MX25 FlexCAN2 03.00.00.00 no no no no no no 64
26 * MX28 FlexCAN2 03.00.04.00 yes yes no no no no 64
27 * MX35 FlexCAN2 03.00.00.00 no no no no no no 64
28 * MX53 FlexCAN2 03.00.00.00 yes no no no no no 64
29 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes no 64
30 * MX8QM FlexCAN3 03.00.23.00 yes yes no no yes yes 64
31 * MX8MP FlexCAN3 03.00.17.01 yes yes no yes yes yes 64
32 * VF610 FlexCAN3 ? no yes no yes yes? no 64
33 * LS1021A FlexCAN2 03.00.04.00 no yes no no yes no 64
34 * LX2160A FlexCAN3 03.00.23.00 no yes no yes yes yes 64
[all …]
/linux/include/xen/interface/
H A Dcallback.h28 /* x86/64 hypervisor: Syscall by 64-bit guest app ('64-on-64-on-64'). */
42 * - 32-bit hypervisor: with the supervisor_mode_kernel feature enabled
43 * - 64-bit hypervisor: 32-bit guest applications on Intel CPUs
44 * ('32-on-32-on-64', '32-on-64-on-64')
45 * [nb. also 64-bit guest applications on Intel CPUs
46 * ('64-on-64-on-64'), but syscall is preferred]
51 * x86/64 hypervisor: Syscall by 32-bit guest app on AMD CPUs
52 * ('32-on-32-on-64', '32-on-64-on-64')
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-fau.h57 * bit will be set. Otherwise the value of the register before
67 * bit will be set. Otherwise the value of the register before
77 * bit will be set. Otherwise the value of the register before
87 * bit will be set. Otherwise the value of the register before
97 * the error bit will be set. Otherwise the value of the
124 * - Step by 2 for 16 bit access.
125 * - Step by 4 for 32 bit access.
126 * - Step by 8 for 64 bit access.
144 * - Step by 2 for 16 bit access.
145 * - Step by 4 for 32 bit access.
[all …]
/linux/lib/crc/x86/
H A Dcrc-pclmul-template.S76 // Broadcast an aligned 128-bit mem operand to all 128-bit lanes of a vector
89 // is msb-first use \bswap_mask to reflect the bytes within each 128-bit lane.
91 .if \vl < 64
103 .if \vl < 64
110 .if \vl < 64
118 // The x^0..x^63 terms, i.e. poly128 mod x^64, i.e. the physically low qword for
122 // The x^64..x^127 terms, i.e. floor(poly128 / x^64), i.e. the physically high
126 // Multiply the given \src1_terms of each 128-bit lane of \src1 by the given
127 // \src2_terms of each 128-bit lane of \src2, and write the result(s) to \dst.
164 // into all 128-bit lanes of the vector register CONSTS.
[all …]
/linux/arch/x86/um/
H A DKconfig15 config 64BIT config
16 bool "64-bit kernel" if "$(SUBARCH)" = "x86"
20 def_bool !64BIT
29 def_bool 64BIT
33 def_bool !64BIT
36 def_bool !64BIT
/linux/arch/mips/kernel/
H A Dunaligned.c337 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
338 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
339 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
340 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
341 * instructions on 32-bit kernels. in emulate_load_store_insn()
354 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
360 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
361 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
362 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
363 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
[all …]
/linux/lib/tests/
H A Dffs_kunit.c32 /* Single bit patterns - powers of 2 */
33 {0x00000001, 1, 1, "bit 0 set"},
34 {0x00000002, 2, 2, "bit 1 set"},
35 {0x00000004, 3, 3, "bit 2 set"},
36 {0x00000008, 4, 4, "bit 3 set"},
37 {0x00000010, 5, 5, "bit 4 set"},
38 {0x00000020, 6, 6, "bit 5 set"},
39 {0x00000040, 7, 7, "bit 6 set"},
40 {0x00000080, 8, 8, "bit 7 set"},
41 {0x00000100, 9, 9, "bit 8 set"},
[all …]
/linux/lib/crc/s390/
H A Dcrc32be-vx.c9 * bit first (BE).
34 * R1 = x4*128+64 mod P(x)
36 * R3 = x128+64 mod P(x)
41 * Barret reduction constant, u, is defined as floor(x**64 / P(x)).
72 * @size: Size of the buffer, must be 64 bytes or greater.
89 /* Load a 64-byte data chunk and XOR with CRC */ in crc32_be_vgfm_16()
92 buf += 64; in crc32_be_vgfm_16()
93 size -= 64; in crc32_be_vgfm_16()
95 while (size >= 64) { in crc32_be_vgfm_16()
96 /* Load the next 64-byte data chunk into V5 to V8 */ in crc32_be_vgfm_16()
[all …]
/linux/Documentation/bpf/standardization/
H A Dinstruction-set.rst40 a type's signedness (`S`) and bit width (`N`), respectively.
51 .. table:: Meaning of bit-width notation
54 N Bit width
59 64 64 bits
63 For example, `u32` is a type whose valid values are all the 32-bit unsigned
64 numbers and `s16` is a type whose valid values are all the 16-bit signed
74 * be16: Takes an unsigned 16-bit number and converts it between
77 * be32: Takes an unsigned 32-bit number and converts it between
79 * be64: Takes an unsigned 64-bit number and converts it between
81 * bswap16: Takes an unsigned 16-bit number in either big- or little-endian
[all …]
/linux/Documentation/bpf/
H A Dclassic_vs_extended.rst16 pointer. Since 64-bit CPUs are passing arguments to functions via registers
25 64-bit architectures.
27 On 32-bit architectures JIT may map programs that use only 32-bit arithmetic
35 - Register width increases from 32-bit to 64-bit:
37 Still, the semantics of the original 32-bit ALU operations are preserved
38 via 32-bit subregisters. All eBPF registers are 64-bit with 32-bit lower
39 subregisters that zero-extend into 64-bit if they are being written to.
43 32-bit architectures run 64-bit eBPF programs via interpreter.
44 Their JITs may convert BPF programs that only use 32-bit subregisters into
47 Operation is 64-bit, because on 64-bit architectures, pointers are also
[all …]
/linux/arch/x86/math-emu/
H A Dwm_shrx.S6 | 64 bit right shift functions |
27 | Shifts the 64 bit quantity pointed to by the first arg (arg1) |
29 | Forms a 96 bit quantity from the 64 bit arg and eax: |
30 | [ 64 bit arg ][ eax ] |
33 | Results returned in the 64 bit arg and eax. |
61 cmpl $64,%ecx
79 subb $64,%cl
104 | Shifts the 64 bit quantity pointed to by the first arg (arg1) |
106 | Forms a 96 bit quantity from the 64 bit arg and eax: |
107 | [ 64 bit arg ][ eax ] |
[all …]
/linux/arch/mips/
H A DKconfig5 select ARCH_32BIT_OFF_T if !64BIT
10 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
15 select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
23 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
36 select GENERIC_ATOMIC64 if !64BIT
98 select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
103 select MODULES_USE_ELF_RELA if MODULES && 64BIT
110 select HAVE_ARCH_KCSAN if 64BIT
362 select CPU_DADDI_WORKAROUNDS if 64BIT
363 select CPU_R4000_WORKAROUNDS if 64BIT
[all …]

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