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/linux/arch/loongarch/
H A DKconfig23 select ARCH_HAS_KERNEL_FPU_SUPPORT if 64BIT && CPU_HAS_FPU
27 select ARCH_HAS_PTE_SPECIAL if 64BIT
65 select ARCH_SUPPORTS_HUGETLBFS if 64BIT
70 select ARCH_HAS_PTE_PROTNONE if 64BIT
84 select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP if 64BIT
92 select GENERIC_ATOMIC64 if 32BIT
99 select GENERIC_GETTIMEOFDAY if 64BIT
116 select HAVE_ALIGNED_STRUCT_PAGE if 64BIT
118 select HAVE_ARCH_BITREVERSE if 64BIT && BITREVERSE
121 select HAVE_ARCH_KASAN if 64BIT
[all …]
/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn23xx_pf_regs.h74 /* 2 scatch registers (64-bit) */
80 /* 1 registers (64-bit) - SLI_CTL_STATUS */
83 /* SLI Packet Input Jabber Register (64 bit register)
117 /* 4 registers (64-bit) for mapping IOQs to MACs(PEMs)-
122 /*1 register (64-bit) to determine whether IOQs are in reset. */
141 /* Starting bit of the TRS field in CN23XX_SLI_PKT_MAC_RINFO64 register */
143 /* Starting bit of SRN field in CN23XX_SLI_PKT_MAC_RINFO64 register */
145 /* Starting bit of RPVF field in CN23XX_SLI_PKT_MAC_RINFO64 register */
147 /* Starting bit of NVFS field in CN23XX_SLI_PKT_MAC_RINFO64 register */
152 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
[all …]
H A Dcn23xx_vf_regs.h52 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
55 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
58 /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
61 /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
64 /* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data &
87 #define CN23XX_PKT_INPUT_CTL_MAC_NUM BIT(29)
92 #define CN23XX_PKT_INPUT_CTL_IS_64B BIT(24)
93 #define CN23XX_PKT_INPUT_CTL_RST BIT(23)
94 #define CN23XX_PKT_INPUT_CTL_QUIET BIT(28)
95 #define CN23XX_PKT_INPUT_CTL_RING_ENB BIT(22)
[all …]
H A Dcn66xx_regs.h89 /* 1 register (32-bit) to enable Input queues */
92 /* 1 register (32-bit) to enable Output queues */
95 /* 1 register (32-bit) to determine whether Output queues are in reset. */
98 /* 1 register (32-bit) to determine whether Input queues are in reset. */
103 /* 1 register (32-bit) - instr. size of each input queue. */
121 /* 1 register (64-bit) - Back Pressure for each input queue - SLI_PKT0_IN_BP */
127 /* 1 register (32-bit) - ES, RO, NS, Arbitration for Input Queue Data &
132 /* 1 register (64-bit) - Number of instructions to read at one time
137 /* 1 register (64-bit) - Assign Input ring to MAC port
162 #define CN6XXX_INPUT_CTL_ROUND_ROBIN_ARB BIT(22)
[all …]
/linux/arch/riscv/
H A DKconfig7 config 64BIT
10 config 32BIT
41 select ARCH_HAS_KERNEL_FPU_SUPPORT if 64BIT && FPU
62 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE if 64BIT && MMU
73 select ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS if 64BIT && MMU
80 select ARCH_USE_CMPXCHG_LOCKREF if 64BI
[all...]
/linux/drivers/net/ethernet/broadcom/
H A Dtg3.h21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
285 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
286 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
307 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
308 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
309 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
310 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
311 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
[all …]
/linux/include/linux/
H A Dnfs4.h147 OP_LAYOUTERROR = 64,
350 FATTR4_LAYOUT_TYPES = 64,
402 * attribute bits within 32-bit word boundaries.
406 #define FATTR4_WORD0_SUPPORTED_ATTRS BIT(FATTR4_SUPPORTED_ATTRS)
407 #define FATTR4_WORD0_TYPE BIT(FATTR4_TYPE)
408 #define FATTR4_WORD0_FH_EXPIRE_TYPE BIT(FATTR4_FH_EXPIRE_TYPE)
409 #define FATTR4_WORD0_CHANGE BIT(FATTR4_CHANGE)
410 #define FATTR4_WORD0_SIZE BIT(FATTR4_SIZE)
411 #define FATTR4_WORD0_LINK_SUPPORT BIT(FATTR4_LINK_SUPPORT)
412 #define FATTR4_WORD0_SYMLINK_SUPPORT BIT(FATTR4_SYMLINK_SUPPORT)
[all …]
/linux/include/xen/interface/
H A Dcallback.h28 /* x86/64 hypervisor: Syscall by 64-bit guest app ('64-on-64-on-64'). */
42 * - 32-bit hypervisor: with the supervisor_mode_kernel feature enabled
43 * - 64-bit hypervisor: 32-bit guest applications on Intel CPUs
44 * ('32-on-32-on-64', '32-on-64-on-64')
45 * [nb. also 64-bit guest applications on Intel CPUs
46 * ('64-on-64-on-64'), but syscall is preferred]
51 * x86/64 hypervisor: Syscall by 32-bit guest app on AMD CPUs
52 * ('32-on-32-on-64', '32-on-64-on-64')
/linux/drivers/net/can/flexcan/
H A Dflexcan.h25 * MX25 FlexCAN2 03.00.00.00 no no no no no no 64
26 * MX28 FlexCAN2 03.00.04.00 yes yes no no no no 64
27 * MX35 FlexCAN2 03.00.00.00 no no no no no no 64
28 * MX53 FlexCAN2 03.00.00.00 yes no no no no no 64
29 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes no 64
30 * MX8QM FlexCAN3 03.00.23.00 yes yes no no yes yes 64
31 * MX8MP FlexCAN3 03.00.17.01 yes yes no yes yes yes 64
32 * VF610 FlexCAN3 ? no yes no yes yes? no 64
33 * LS1021A FlexCAN2 03.00.04.00 no yes no no yes no 64
34 * LX2160A FlexCAN3 03.00.23.00 no yes no yes yes yes 64
[all …]
/linux/arch/x86/kvm/vmx/
H A Dvmx_ops.h23 * for 64-bit targets. Preserving all registers allows the VMREAD inline asm
29 * 64-bit targets.
46 "16-bit accessor invalid for 64-bit field"); in vmcs_check16()
48 "16-bit accessor invalid for 64-bit high field"); in vmcs_check16()
50 "16-bit accessor invalid for 32-bit field"); in vmcs_check16()
52 "16-bit accessor invalid for natural width field"); in vmcs_check16()
58 "32-bit accessor invalid for 16-bit field"); in vmcs_check32()
60 "32-bit accessor invalid for 64-bit field"); in vmcs_check32()
62 "32-bit accessor invalid for 64-bit high field"); in vmcs_check32()
64 "32-bit accessor invalid for natural width field"); in vmcs_check32()
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-fau.h57 * bit will be set. Otherwise the value of the register before
67 * bit will be set. Otherwise the value of the register before
77 * bit will be set. Otherwise the value of the register before
87 * bit will be set. Otherwise the value of the register before
97 * the error bit will be set. Otherwise the value of the
124 * - Step by 2 for 16 bit access.
125 * - Step by 4 for 32 bit access.
126 * - Step by 8 for 64 bit access.
144 * - Step by 2 for 16 bit access.
145 * - Step by 4 for 32 bit access.
[all …]
/linux/lib/crc/x86/
H A Dcrc-pclmul-template.S76 // Broadcast an aligned 128-bit mem operand to all 128-bit lanes of a vector
89 // is msb-first use \bswap_mask to reflect the bytes within each 128-bit lane.
91 .if \vl < 64
103 .if \vl < 64
110 .if \vl < 64
118 // The x^0..x^63 terms, i.e. poly128 mod x^64, i.e. the physically low qword for
122 // The x^64..x^127 terms, i.e. floor(poly128 / x^64), i.e. the physically high
126 // Multiply the given \src1_terms of each 128-bit lane of \src1 by the given
127 // \src2_terms of each 128-bit lane of \src2, and write the result(s) to \dst.
164 // into all 128-bit lanes of the vector register CONSTS.
[all …]
/linux/tools/testing/vma/tests/
H A Dvma.c111 int bit; in test_vma_flags_cleared()
118 for (bit = 0; bit < BITS_PER_LONG; bit++) {
119 vma_flags_t mask = mk_vma_flags(bit);
121 legacy_flags |= (1UL << bit);
124 vma_flags_set(&flags, bit); in test_vma_flags_word()
132 vma_set_flags(&vma, bit); in test_vma_flags_word()
138 vma_desc_set_flags(&desc, bit); in test_vma_flags_word()
169 #if NUM_VMA_FLAG_BITS > 64 in test_vma_flags_test()
60 int bit; test_vma_flags_unchanged() local
[all...]
/linux/arch/mips/kernel/
H A Dunaligned.c337 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
338 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
339 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
340 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
341 * instructions on 32-bit kernels. in emulate_load_store_insn()
354 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
360 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
361 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
362 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
363 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
[all …]
/linux/lib/tests/
H A Dffs_kunit.c32 /* Single bit patterns - powers of 2 */
33 {0x00000001, 1, 1, "bit 0 set"},
34 {0x00000002, 2, 2, "bit 1 set"},
35 {0x00000004, 3, 3, "bit 2 set"},
36 {0x00000008, 4, 4, "bit 3 set"},
37 {0x00000010, 5, 5, "bit 4 set"},
38 {0x00000020, 6, 6, "bit 5 set"},
39 {0x00000040, 7, 7, "bit 6 set"},
40 {0x00000080, 8, 8, "bit 7 set"},
41 {0x00000100, 9, 9, "bit 8 set"},
[all …]
/linux/tools/sched_ext/include/scx/
H A Dcid.bpf.h41 #define CMASK_NR_WORDS(nr_cids) ((u32)(((u64)(nr_cids) + 63) / 64 + 1))
50 return (u64 __arena *)&m->bits[cid / 64 - m->base / 64]; in __cmask_word()
116 u32 last_word = ((base & 63) + nr_cids - 1) / 64; in cmask_reframe()
146 u64 bit, old, new; in cmask_set() local
152 bit = BIT_U64(cid & 63); in cmask_set()
155 if (old & bit) in cmask_set()
157 new = old | bit; in cmask_set()
167 u64 bit, old, new; in cmask_clear() local
173 bit = BIT_U64(cid & 63); in cmask_clear()
176 if (!(old & bit)) in cmask_clear()
[all …]
/linux/lib/crc/s390/
H A Dcrc32be-vx.c9 * bit first (BE).
34 * R1 = x4*128+64 mod P(x)
36 * R3 = x128+64 mod P(x)
41 * Barret reduction constant, u, is defined as floor(x**64 / P(x)).
72 * @size: Size of the buffer, must be 64 bytes or greater.
89 /* Load a 64-byte data chunk and XOR with CRC */ in crc32_be_vgfm_16()
92 buf += 64; in crc32_be_vgfm_16()
93 size -= 64; in crc32_be_vgfm_16()
95 while (size >= 64) { in crc32_be_vgfm_16()
96 /* Load the next 64-byte data chunk into V5 to V8 */ in crc32_be_vgfm_16()
[all …]
/linux/Documentation/bpf/
H A Dclassic_vs_extended.rst16 pointer. Since 64-bit CPUs are passing arguments to functions via registers
25 64-bit architectures.
27 On 32-bit architectures JIT may map programs that use only 32-bit arithmetic
35 - Register width increases from 32-bit to 64-bit:
37 Still, the semantics of the original 32-bit ALU operations are preserved
38 via 32-bit subregisters. All eBPF registers are 64-bit with 32-bit lower
39 subregisters that zero-extend into 64-bit if they are being written to.
43 32-bit architectures run 64-bit eBPF programs via interpreter.
44 Their JITs may convert BPF programs that only use 32-bit subregisters into
47 Operation is 64-bit, because on 64-bit architectures, pointers are also
[all …]
/linux/Documentation/bpf/standardization/
H A Dinstruction-set.rst40 a type's signedness (`S`) and bit width (`N`), respectively.
51 .. table:: Meaning of bit-width notation
54 N Bit width
59 64 64 bits
63 For example, `u32` is a type whose valid values are all the 32-bit unsigned
64 numbers and `s16` is a type whose valid values are all the 16-bit signed
74 * be16: Takes an unsigned 16-bit number and converts it between
77 * be32: Takes an unsigned 32-bit number and converts it between
79 * be64: Takes an unsigned 64-bit number and converts it between
81 * bswap16: Takes an unsigned 16-bit number in either big- or little-endian
[all …]
/linux/drivers/net/ethernet/cavium/
H A DKconfig18 depends on 64BIT && PCI
31 depends on 64BIT && PCI
37 depends on 64BIT && PCI
47 depends on 64BIT && PCI
56 depends on 64BIT && PCI
70 depends on 64BIT && PCI
97 depends on 64BIT && PCI_MSI
/linux/arch/powerpc/boot/dts/
H A Dmicrowatt.dts54 hwcap-bit-nr = <1>;
75 hfscr-bit-nr = <0>;
76 hwcap-bit-nr = <27>;
84 hfscr-bit-nr = <13>;
85 fscr-bit-nr = <13>;
93 hfscr-bit-nr = <8>;
94 fscr-bit-nr = <8>;
99 hwcap-bit-nr = <58>;
111 fscr-bit-nr = <12>;
112 hwcap-bit-nr = <52>;
[all …]
/linux/arch/x86/include/uapi/asm/
H A Ducontext.h14 * UC_SIGCONTEXT_SS will be set when delivering 64-bit or x32 signals on
20 * when delivering a signal that came from 64-bit code.
25 * saved CS is not 64-bit)
28 * new SS = a flat 32-bit data segment
32 * - Legacy programs that construct a 64-bit sigcontext from scratch
38 * the saved CS to a 64-bit segment. These DOSEMU versions expect
39 * sigreturn to send them back to 64-bit mode without killing them,
/linux/drivers/net/wireless/marvell/mwifiex/
H A Ddecl.h23 #define MWIFIEX_DMA_ALIGN_SZ 64
24 #define MWIFIEX_RX_HEADROOM 64
47 #define HOST_MLME_AUTH_PENDING BIT(0)
48 #define HOST_MLME_AUTH_DONE BIT(1)
50 #define HOST_MLME_MGMT_MASK (BIT(IEEE80211_STYPE_AUTH >> 4) | \
51 BIT(IEEE80211_STYPE_DEAUTH >> 4) | \
52 BIT(IEEE80211_STYPE_DISASSOC >> 4))
61 #define MWIFIEX_STA_AMPDU_DEF_TXWINSIZE 64
62 #define MWIFIEX_STA_AMPDU_DEF_RXWINSIZE 64
70 #define MWIFIEX_11AC_STA_AMPDU_DEF_TXWINSIZE 64
[all …]
/linux/arch/mips/net/
H A Dbpf_jit_comp64.c4 * Implementation of JIT functions for 64-bit CPUs.
33 /* Extra 64-bit eBPF registers used by JIT */
42 (BIT(MIPS_R_S0) | \
43 BIT(MIPS_R_S1) | \
44 BIT(MIPS_R_S2) | \
45 BIT(MIPS_R_S3) | \
46 BIT(MIPS_R_S4) | \
47 BIT(MIPS_R_S5) | \
48 BIT(MIPS_R_S6) | \
49 BIT(MIPS_R_S7) | \
[all …]
/linux/lib/
H A Diomap_copy.c10 * __iowrite32_copy - copy data to MMIO space, in 32-bit units
11 * @to: destination, in MMIO space (must be 32-bit aligned)
12 * @from: source (must be 32-bit aligned)
13 * @count: number of 32-bit quantities to copy
33 * __ioread32_copy - copy data from MMIO space, in 32-bit units
34 * @to: destination (must be 32-bit aligned)
35 * @from: source, in MMIO space (must be 32-bit aligned)
36 * @count: number of 32-bit quantities to copy
54 * __iowrite64_copy - copy data to MMIO space, in 64-bit or 32-bit units
55 * @to: destination, in MMIO space (must be 64-bit aligned)
[all …]

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