| /linux/include/linux/ |
| H A D | math64.h | 10 #if BITS_PER_LONG == 64
16 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
17 * @dividend: unsigned 64bit dividend
18 * @divisor: unsigned 32bit divisor
19 * @remainder: pointer to unsigned 32bit remainder
23 * This is commonly provided by 32bit archs to provide an optimized 64bit
33 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
34 * @dividend: signed 64bit dividend
35 * @divisor: signed 32bit divisor
36 * @remainder: pointer to signed 32bit remainder
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| H A D | exportfs.h | 33 * 32bit inode number, 32 bit generation number.
38 * 32bit inode number, 32 bit generation number,
39 * 32 bit parent directory inode number.
44 * 64 bit object ID, 64 bit root object ID,
45 * 32 bit generation number.
50 * 64 bit object ID, 64 bit root object ID,
51 * 32 bit generation number,
52 * 64 bit parent object ID, 32 bit parent generation.
57 * 64 bit object ID, 64 bit root object ID,
58 * 32 bit generation number,
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| /linux/drivers/mtd/nand/raw/ |
| H A D | nand_ids.c | 29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNQGAMA 64G 3.3V 8-bit",
50 {"SDTNRGAMA 64G 3.3V 8-bit",
53 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
[all …]
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| /linux/arch/x86/crypto/ |
| H A D | Kconfig | 7 depends on X86 && 64BIT
30 Architecture: x86 (32-bit and 64-bit) using:
34 Some algorithm implementations are supported only in 64-bit builds,
39 depends on X86 && 64BIT
51 depends on X86 && 64BIT
62 depends on X86 && 64BIT
76 depends on X86 && 64BIT
87 depends on X86 && 64BIT
104 depends on X86 && 64BIT
122 depends on X86 && 64BIT
[all …]
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| /linux/lib/ |
| H A D | atomic64_test.c | 20 #define TEST(bit, op, c_op, val) \ argument
22 atomic##bit##_set(&v, v0); \
24 atomic##bit##_##op(val, &v); \
26 WARN(atomic##bit##_read(&v) != r, "%Lx != %Lx\n", \
27 (unsigned long long)atomic##bit##_read(&v), \
33 * @test should be a macro accepting parameters (bit, op, ...)
36 #define FAMILY_TEST(test, bit, op, args...) \ argument
38 test(bit, op, ##args); \
39 test(bit, op##_acquire, ##args); \
40 test(bit, op##_release, ##args); \
[all …]
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| /linux/arch/parisc/ |
| H A D | Kconfig | 5 select ARCH_32BIT_OFF_T if !64BIT
20 select ARCH_SPLIT_ARG64 if !64BIT
40 select GENERIC_ATOMIC64 if !64BIT
90 select HAVE_FUNCTION_DESCRIPTORS if 64BIT
124 select GENERIC_BUG_RELATIVE_POINTERS if 64BIT
143 default 18 if 64BIT
150 default 18 if 64BIT
177 default 3 if 64BIT && PARISC_PAGE_SIZE_4KB
191 that can run on all 32-bit PA CPUs (albeit not optimally fast),
194 Specifying "PA8000" here will allow you to select a 64-bit kernel
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| /linux/drivers/net/ethernet/cavium/liquidio/ |
| H A D | cn23xx_pf_regs.h | 74 /* 2 scatch registers (64-bit) */
80 /* 1 registers (64-bit) - SLI_CTL_STATUS */
83 /* SLI Packet Input Jabber Register (64 bit register)
117 /* 4 registers (64-bit) for mapping IOQs to MACs(PEMs)-
122 /*1 register (64-bit) to determine whether IOQs are in reset. */
141 /* Starting bit of the TRS field in CN23XX_SLI_PKT_MAC_RINFO64 register */
143 /* Starting bit of SRN field in CN23XX_SLI_PKT_MAC_RINFO64 register */
145 /* Starting bit of RPVF field in CN23XX_SLI_PKT_MAC_RINFO64 register */
147 /* Starting bit of NVFS field in CN23XX_SLI_PKT_MAC_RINFO64 register */
152 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
[all …]
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| H A D | cn23xx_vf_regs.h | 52 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
55 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
58 /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
61 /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
64 /* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data &
87 #define CN23XX_PKT_INPUT_CTL_MAC_NUM BIT(29)
92 #define CN23XX_PKT_INPUT_CTL_IS_64B BIT(24)
93 #define CN23XX_PKT_INPUT_CTL_RST BIT(23)
94 #define CN23XX_PKT_INPUT_CTL_QUIET BIT(28)
95 #define CN23XX_PKT_INPUT_CTL_RING_ENB BIT(22)
[all …]
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| H A D | cn66xx_regs.h | 89 /* 1 register (32-bit) to enable Input queues */
92 /* 1 register (32-bit) to enable Output queues */
95 /* 1 register (32-bit) to determine whether Output queues are in reset. */
98 /* 1 register (32-bit) to determine whether Input queues are in reset. */
103 /* 1 register (32-bit) - instr. size of each input queue. */
121 /* 1 register (64-bit) - Back Pressure for each input queue - SLI_PKT0_IN_BP */
127 /* 1 register (32-bit) - ES, RO, NS, Arbitration for Input Queue Data &
132 /* 1 register (64-bit) - Number of instructions to read at one time
137 /* 1 register (64-bit) - Assign Input ring to MAC port
162 #define CN6XXX_INPUT_CTL_ROUND_ROBIN_ARB BIT(22)
[all …]
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| /linux/arch/riscv/ |
| H A D | Kconfig | 7 config 64BIT config
10 config 32BIT
36 select ARCH_HAS_KERNEL_FPU_SUPPORT if 64BIT && FPU
43 select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU
55 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE if 64BIT && MMU
70 select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
79 select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
95 select GENERIC_ATOMIC64 if !64BIT
114 select GENERIC_TIME_VSYSCALL if MMU && 64BIT
120 select HAVE_ARCH_HUGE_VMAP if MMU && 64BIT
[all …]
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| /linux/drivers/net/ethernet/broadcom/ |
| H A D | tg3.h | 21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
285 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
286 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
307 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
308 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
309 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
310 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
311 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
[all …]
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| /linux/drivers/acpi/acpica/ |
| H A D | tbfadt.c | 166 * Bit width field in the GAS is only one byte long, 255 max. in acpi_tb_init_generic_address()
178 "%s - 32-bit FADT register is too long (%u bytes, %u bits) " in acpi_tb_init_generic_address()
188 * The 64-bit Address field is non-aligned in the byte packed in acpi_tb_init_generic_address()
206 * address32 - 32-bit address of the register
207 * address64 - 64-bit address of the register
209 * RETURN: The resolved 64-bit address
211 * DESCRIPTION: Select between 32-bit and 64-bit versions of addresses within
217 * the 32-bit and 64-bit address fields (FIRMWARE_CTRL/X_FIRMWARE_CTRL and
222 * By default, as per the ACPICA specification, a valid 64-bit address is
223 * used regardless of the value of the 32-bit address. However, this
[all …]
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| /linux/arch/x86/um/ |
| H A D | Kconfig | 14 config 64BIT config
15 bool "64-bit kernel" if "$(SUBARCH)" = "x86"
19 def_bool !64BIT
28 def_bool 64BIT
32 bool "Three-level pagetables" if !64BIT
33 default 64BIT
39 However, this it experimental on 32-bit architectures, so if unsure say
40 N (on x86-64 it's automatically enabled, instead, as it's safe there).
43 def_bool !64BIT
46 def_bool !64BIT
|
| /linux/arch/s390/include/asm/ |
| H A D | elf.h | 13 #define R_390_8 1 /* Direct 8 bit. */
14 #define R_390_12 2 /* Direct 12 bit. */
15 #define R_390_16 3 /* Direct 16 bit. */
16 #define R_390_32 4 /* Direct 32 bit. */
17 #define R_390_PC32 5 /* PC relative 32 bit. */
18 #define R_390_GOT12 6 /* 12 bit GOT offset. */
19 #define R_390_GOT32 7 /* 32 bit GOT offset. */
20 #define R_390_PLT32 8 /* 32 bit PC relative PLT address. */
25 #define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */
26 #define R_390_GOTPC 14 /* 32 bit PC rel. offset to GOT. */
[all …]
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| /linux/include/xen/interface/ |
| H A D | callback.h | 28 /* x86/64 hypervisor: Syscall by 64-bit guest app ('64-on-64-on-64'). */
42 * - 32-bit hypervisor: with the supervisor_mode_kernel feature enabled
43 * - 64-bit hypervisor: 32-bit guest applications on Intel CPUs
44 * ('32-on-32-on-64', '32-on-64-on-64')
45 * [nb. also 64-bit guest applications on Intel CPUs
46 * ('64-on-64-on-64'), but syscall is preferred]
51 * x86/64 hypervisor: Syscall by 32-bit guest app on AMD CPUs
52 * ('32-on-32-on-64', '32-on-64-on-64')
|
| /linux/drivers/net/can/flexcan/ |
| H A D | flexcan.h | 25 * MX25 FlexCAN2 03.00.00.00 no no no no no no 64
26 * MX28 FlexCAN2 03.00.04.00 yes yes no no no no 64
27 * MX35 FlexCAN2 03.00.00.00 no no no no no no 64
28 * MX53 FlexCAN2 03.00.00.00 yes no no no no no 64
29 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes no 64
30 * MX8QM FlexCAN3 03.00.23.00 yes yes no no yes yes 64
31 * MX8MP FlexCAN3 03.00.17.01 yes yes no yes yes yes 64
32 * VF610 FlexCAN3 ? no yes no yes yes? no 64
33 * LS1021A FlexCAN2 03.00.04.00 no yes no no yes no 64
34 * LX2160A FlexCAN3 03.00.23.00 no yes no yes yes yes 64
[all …]
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| /linux/arch/x86/kvm/vmx/ |
| H A D | vmx_ops.h | 23 * for 64-bit targets. Preserving all registers allows the VMREAD inline asm
29 * 64-bit targets.
46 "16-bit accessor invalid for 64-bit field"); in vmcs_check16()
48 "16-bit accessor invalid for 64-bit high field"); in vmcs_check16()
50 "16-bit accessor invalid for 32-bit field"); in vmcs_check16()
52 "16-bit accessor invalid for natural width field"); in vmcs_check16()
58 "32-bit accessor invalid for 16-bit field"); in vmcs_check32()
60 "32-bit accessor invalid for 64-bit field"); in vmcs_check32()
62 "32-bit accessor invalid for 64-bit high field"); in vmcs_check32()
64 "32-bit accessor invalid for natural width field"); in vmcs_check32()
[all …]
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| /linux/arch/mips/include/asm/ |
| H A D | mips-cm.h | 52 * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
53 * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
58 * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
143 GCR_ACCESSOR_RO(64, 0x000, config)
151 GCR_ACCESSOR_RW(64, 0x008, base)
179 #define CM_GCR_ERR_CONTROL_L2_ECC_EN BIT(1)
180 #define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT BIT(0)
183 GCR_ACCESSOR_RW(64, 0x040, error_mask)
186 GCR_ACCESSOR_RW(64, 0x048, error_cause)
192 GCR_ACCESSOR_RW(64, 0x050, error_addr)
[all …]
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| /linux/lib/math/ |
| H A D | div64.c | 10 * Generic C version of 64bit/32bit division and modulo, with
11 * 64bit result and 32bit remainder.
28 /* Not needed on 64bit architectures */
39 /* Reduce the thing a bit first */ in __div64_32()
88 * div64_u64_rem - unsigned 64bi
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| /linux/arch/mips/include/asm/octeon/ |
| H A D | cvmx-fau.h | 57 * bit will be set. Otherwise the value of the register before
67 * bit will be set. Otherwise the value of the register before
77 * bit will be set. Otherwise the value of the register before
87 * bit will be set. Otherwise the value of the register before
97 * the error bit will be set. Otherwise the value of the
124 * - Step by 2 for 16 bit access.
125 * - Step by 4 for 32 bit access.
126 * - Step by 8 for 64 bit access.
144 * - Step by 2 for 16 bit access.
145 * - Step by 4 for 32 bit access.
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| /linux/Documentation/arch/arm64/ |
| H A D | asymmetric-32bit.rst | 2 Asymmetric 32-bit SoCs
7 This document describes the impact of asymmetric 32-bit SoCs on the
8 execution of 32-bit (``AArch32``) applications.
16 of the CPUs are capable of executing 32-bit user applications. On such
19 ``execve(2)`` of 32-bit ELF binaries, with the latter returning
21 64-bit-only CPU, then the onlining operation fails and the new CPU is
25 running legacy 32-bit binaries. Unsurprisingly, that doesn't work very
28 It seems inevitable that future SoCs will drop 32-bit support
30 run 32-bit code on one of these transitionary platforms then you would
38 allowing 32-bit tasks to run on an asymmetric 32-bit system requires an
[all …]
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| /linux/arch/mips/kernel/ |
| H A D | unaligned.c | 337 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
338 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
339 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
340 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
341 * instructions on 32-bit kernels. in emulate_load_store_insn()
354 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
360 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
361 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
362 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
363 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
[all …]
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| /linux/arch/s390/crypto/ |
| H A D | crc32be-vx.c | 9 * bit first (BE).
34 * R1 = x4*128+64 mod P(x)
36 * R3 = x128+64 mod P(x)
41 * Barret reduction constant, u, is defined as floor(x**64 / P(x)).
72 * @size: Size of the buffer, must be 64 bytes or greater.
89 /* Load a 64-byte data chunk and XOR with CRC */ in crc32_be_vgfm_16()
92 buf += 64; in crc32_be_vgfm_16()
93 size -= 64; in crc32_be_vgfm_16()
95 while (size >= 64) { in crc32_be_vgfm_16()
96 /* Load the next 64-byte data chunk into V5 to V8 */ in crc32_be_vgfm_16()
[all …]
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| /linux/Documentation/bpf/standardization/ |
| H A D | instruction-set.rst | 40 a type's signedness (`S`) and bit width (`N`), respectively.
51 .. table:: Meaning of bit-width notation
54 N Bit width
59 64 64 bits
63 For example, `u32` is a type whose valid values are all the 32-bit unsigned
64 numbers and `s16` is a type whose valid values are all the 16-bit signed
74 * be16: Takes an unsigned 16-bit number and converts it between
77 * be32: Takes an unsigned 32-bit number and converts it between
79 * be64: Takes an unsigned 64-bit number and converts it between
81 * bswap16: Takes an unsigned 16-bit number in either big- or little-endian
[all …]
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| /linux/Documentation/bpf/ |
| H A D | classic_vs_extended.rst | 16 pointer. Since 64-bit CPUs are passing arguments to functions via registers
25 64-bit architectures.
27 On 32-bit architectures JIT may map programs that use only 32-bit arithmetic
35 - Register width increases from 32-bit to 64-bit:
37 Still, the semantics of the original 32-bit ALU operations are preserved
38 via 32-bit subregisters. All eBPF registers are 64-bit with 32-bit lower
39 subregisters that zero-extend into 64-bit if they are being written to.
43 32-bit architectures run 64-bit eBPF programs via interpreter.
44 Their JITs may convert BPF programs that only use 32-bit subregisters into
47 Operation is 64-bit, because on 64-bit architectures, pointers are also
[all …]
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