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/freebsd/usr.sbin/bhyve/amd64/
H A Dvga.c46 #define KB (1024UL) macro
222 data = (((sc->vga_ram[offset + 0 * 64*KB] >> bit) & 0x1) << 0) | in vga_get_pixel()
223 (((sc->vga_ram[offset + 1 * 64*KB] >> bit) & 0x1) << 1) | in vga_get_pixel()
224 (((sc->vga_ram[offset + 2 * 64*KB] >> bit) & 0x1) << 2) | in vga_get_pixel()
225 (((sc->vga_ram[offset + 3 * 64*KB] >> bit) & 0x1) << 3); in vga_get_pixel()
269 ch = sc->vga_ram[offset + 0 * 64*KB]; in vga_get_text_pixel()
270 attr = sc->vga_ram[offset + 1 * 64*KB]; in vga_get_text_pixel()
293 font = sc->vga_ram[font_offset + 2 * 64*KB]; in vga_get_text_pixel()
352 offset &= (128 * KB - 1); in vga_mem_rd_handler()
356 * EGA/VGA mode: base 0xa0000 size 64k in vga_mem_rd_handler()
[all …]
H A Drtc.c50 #define m_64KB (64*1024)
83 * 0x34/0x35 - 64KB chunks above 16MB, below 4GB in rtc_init()
84 * 0x5b/0x5c/0x5d - 64KB chunks above 4GB in rtc_init()
/freebsd/usr.sbin/fstyp/
H A Dhammer2_disk.h44 * dmsg_hdr must be 64 bytes
76 * are always 64KB. Logical file buffers are typically 16KB. All data
77 * references utilize 64-bit byte offsets.
85 * to optimize storage efficiency. The minimum fragment size is 1KB.
89 * For the moment the maximum allocation size is HAMMER2_PBUFSIZE (64K),
91 * fragments might be supported in the future (down to 64 bytes is possible),
94 * A full indirect block use supports 512 x 128-byte blockrefs in a 64KB
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/freebsd/sys/x86/x86/
H A Didentcpu.c837 "\003DTES64" /* 64-bit Debug Trace */ in printcpuinfo()
902 "\036LM" /* 64 bit long mode */ in printcpuinfo()
1403 * http://kb.vmware.com/kb/1009458 in identify_hypervisor_cpuid_base()
1859 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); in print_AMD_info()
1862 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); in print_AMD_info()
1891 printf("L2 4KB data TLB: %d entries", in print_AMD_info()
1895 printf("L2 4KB instruction TLB: %d entries", in print_AMD_info()
1899 printf("L2 4KB unified TLB: %d entries", in print_AMD_info()
2003 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); in print_INTEL_TLB()
2009 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); in print_INTEL_TLB()
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/freebsd/sys/dts/arm/
H A Dannapurna-alpine.dts47 d-cache-line-size = <64>; // 64 bytes
48 i-cache-line-size = <64>; // 64 bytes
60 d-cache-line-size = <64>; // 64 bytes
61 i-cache-line-size = <64>; // 64 bytes
73 d-cache-line-size = <64>; // 64 bytes
74 i-cache-line-size = <64>; // 64 bytes
86 d-cache-line-size = <64>; // 64 bytes
87 i-cache-line-size = <64>; // 64 bytes
227 // - IO - IO port space 64KB, reserve 64KB from target memory windows
229 // - 32 bit non prefetchable memory space: 128MB - 64KB
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/freebsd/sys/arm64/include/
H A Dvmparam.h73 #define VM_PHYSSEG_MAX 64
97 * When PAGE_SIZE is 4KB, an allocation size of 16MB is supported in order
98 * to optimize the use of the direct map by UMA. Specifically, a 64-byte
105 * When PAGE_SIZE is 16KB, an allocation size of 32MB is supported. This
124 * Level 0 reservations consist of 16 pages when PAGE_SIZE is 4KB, and 128
125 * pages when PAGE_SIZE is 16KB. Level 1 reservations consist of 32 64KB
126 * pages when PAGE_SIZE is 4KB, and 16 2M pages when PAGE_SIZE is 16KB.
150 * split into 2 regions at each end of the 64 bit address space, with an
184 * 64 bit address space, mostly just for convenience.
324 #define ZERO_REGION_SIZE (64 * 1024) /* 64KB */
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-sm-k26-revA.dts147 compatible = "jedec,spi-nor"; /* 64MB */
160 reg = <0x0 0x80000>; /* 512KB */
166 reg = <0x80000 0x80000>; /* 512KB */
172 reg = <0x100000 0x20000>; /* 128KB */
176 reg = <0x120000 0x20000>; /* 128KB */
180 reg = <0x140000 0xC0000>; /* 768KB */
188 reg = <0xF00000 0x80000>; /* 512KB */
198 reg = <0x1C80000 0x80000>; /* 512KB */
220 reg = <0x2200000 0x20000>; /* 128KB */
224 reg = <0x2220000 0x20000>; /* 128KB */
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/freebsd/sys/dev/ixgbe/
H A Dixgbe_dcb.h42 #define IXGBE_DCB_CREDIT_QUANTUM 64
43 #define IXGBE_DCB_MAX_CREDIT_REFILL 511 /* 0x1FF * 64B = 32704B */
45 #define IXGBE_DCB_MAX_CREDIT 4095 /* Maximum credit supported: 256KB * 1024 / 64B */
47 /* 513 for 32KB TSO packet */
87 u16 data_credits_refill; /* Credit refill amount in 64B granularity */
89 * in 64B granularity.*/
110 /* PBA[0-7] each use 64KB FIFO */
112 /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */
/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Dfacebook-bmc-flash-layout-128.dtsi10 * u-boot partition: 896KB.
18 * u-boot environment variables: 64KB.
26 * image metadata partition (64KB), used by Facebook internal
/freebsd/contrib/ntp/sntp/libevent/cmake/
H A DCheckFileOffsetBits.c3 #define KB ((off_t)1024) macro
4 #define MB ((off_t)1024 * KB)
7 int t2[(((64 * GB -1) % 671088649) == 268434537)
8 && (((TB - (64 * GB -1) + 255) % 1792151290) == 305159546)? 1: -1];
/freebsd/contrib/libevent/cmake/
H A DCheckFileOffsetBits.c3 #define KB ((off_t)1024) macro
4 #define MB ((off_t)1024 * KB)
7 int t2[(((64 * GB -1) % 671088649) == 268434537)
8 && (((TB - (64 * GB -1) + 255) % 1792151290) == 305159546)? 1: -1];
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-370-synology-ds213j.dts278 reg = <0x00000000 0x000c0000>; /* 768KB */
283 reg = <0x000c0000 0x002d0000>; /* 2880KB */
288 reg = <0x00390000 0x00440000>; /* 4250KB */
293 reg = <0x007d0000 0x00010000>; /* 64KB */
298 reg = <0x007e0000 0x00010000>; /* 64KB */
303 reg = <0x007f0000 0x00010000>; /* 64KB */
H A Darmada-xp-synology-ds414.dts295 reg = <0x00000000 0x000d0000>; /* 832KB */
300 reg = <0x000d0000 0x002d0000>; /* 2880KB */
305 reg = <0x003a0000 0x00430000>; /* 4250KB */
310 reg = <0x007d0000 0x00010000>; /* 64KB */
315 reg = <0x007e0000 0x00010000>; /* 64KB */
320 reg = <0x007f0000 0x00010000>; /* 64KB */
/freebsd/contrib/file/magic/Magdir/
H A Dvirtual30 #>(16.Q+64) ubequad x \b, parent name %#llx
64 #>64 ubelong x \b, cksum %#x
83 # VHDX_HEADER signature. 1 header is stored at offset 64KB and the other at 128KB
90 # The Checksum field is a CRC-32C hash over the entire 4 KB structure
116 # Log Entry Length must be a multiple of 4 KB
117 >>>(0x10048.q+8) ulelong/1024 >4 \b, EntryLength %u KB
118 # Log Entry Tail must be a multiple of 4 KB
134 #>>>(0x10048.q+64) ulequad >0 \b, filling %llx
137 # VHDX_REGION_TABLE_HEADER Signature 0x69676572~regi at offset 192 KB and 256 KB
140 # region Checksum. CRC-32C hash over the entire 64-KB table
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/northstar2/
H A Dns2-xmc.dts159 reg = <0x00000000 0x00080000>; /* 512KB */
164 reg = <0x00080000 0x00150000>; /* 1344KB */
169 reg = <0x001e0000 0x00010000>;/* 64KB */
174 reg = <0x001f0000 0x00010000>; /* 64KB */
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dturris1x.dts100 crypto@64 {
274 /* 128 kB for Device Tree Blob */
298 /* 768 kB for Certificates JFFS2 File System */
306 /* 128 kB for U-Boot Environment Variables */
312 /* 768 kB for U-Boot Bootloader Image */
387 * level 64 (between rstcr and watchdog) because
397 priority = <64>;
480 * uses 64kB + 8kB of PCIe MEM. No PCIe IO is used or required.
481 * So allocate 128kB of PCIe MEM for this PCIe bus.
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYBaseInfo.h30 AddrMode32B = 1, // ld32.b, ld32.bs, st32.b, st32.bs, +4kb
31 AddrMode32H = 2, // ld32.h, ld32.hs, st32.h, st32.hs, +8kb
32 AddrMode32WD = 3, // ld32.w, st32.w, ld32.d, st32.d, +16kb
34 AddrMode16H = 5, // ld16.h, +64b
35 AddrMode16W = 6, // ld16.w, +128b or +1kb
36 AddrMode32SDF = 7, // flds, fldd, +1kb
/freebsd/share/man/man4/
H A Dti.463 Either chip can be used in either a 32-bit or 64-bit PCI
211 The default value is 1 which means driver will use full 64bit
248 The default value is 64.
270 The lower 7 bits are used to indicate the ratio in 1/64th increments.
274 68 KB.
276 800 KB.
277 For a 512 KB NIC that number is 300 KB.
378 .It "ti%d: bios thinks we're in a 64 bit slot, but we aren't"
380 a 64-bit PCI slot, but in fact the NIC is in a 32-bit slot.
/freebsd/sys/dev/qlnx/qlnxe/
H A Diwarp_common.h42 #define IWARP_SHARED_QUEUE_PAGE_SIZE (0x8000) //32KB page for Shared Queue Page
43 #define IWARP_SHARED_QUEUE_PAGE_RQ_PBL_OFFSET (0x4000) //First 12KB of Shared Queue Page is reserv…
44 #define IWARP_SHARED_QUEUE_PAGE_RQ_PBL_MAX_SIZE (0x1000) //Max RQ PBL Size is 4KB
46 #define IWARP_SHARED_QUEUE_PAGE_SQ_PBL_MAX_SIZE (0x3000) //Max SQ PBL Size is 12KB
51 #define IWARP_MAX_QPS (64*1024)
/freebsd/sys/powerpc/powerpc/
H A Dgdb_machdep.c58 if (regnum == 64) in gdb_cpu_getreg()
70 if (regnum == 64) in gdb_cpu_getreg()
108 * In both cases, the text segment offset is aligned to 64KB. in gdb_cpu_do_offsets()
113 * 64KB gives the text segment offset. in gdb_cpu_do_offsets()
/freebsd/sys/contrib/openzfs/include/sys/
H A Dbrt_impl.h40 * by a 16bit counter, thus 1TB VDEV requires 128kB of memory: (1TB / 16MB) * 2B
58 * entcounts take 128MB of memory ((64TB / 16MB) * 2B). We can divide this
59 * 128MB array of entcounts into 32kB disk blocks, as we don't want to update
61 * We maintain a bitmap where each 32kB disk block within 128MB entcounts array
64 * that reside on a 32kB disk block (32kB / sizeof (uint16_t)).
141 * (so the whole array is 128kB). We updated bv_entcount[2] and
143 * be set and we will write only first BRT_BLOCKSIZE out of 128kB.
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp56 GISelKnownBits &KB, GISelCSEInfo *CSEInfo,
132 GISelKnownBits &KB, GISelCSEInfo *CSEInfo, in AMDGPUPostLegalizerCombinerImpl() argument
135 : Combiner(MF, CInfo, TPC, &KB, CSEInfo), RuleConfig(RuleConfig), STI(STI), in AMDGPUPostLegalizerCombinerImpl()
137 Helper(Observer, B, /*IsPreLegalize*/ false, &KB, MDT, LI), in AMDGPUPostLegalizerCombinerImpl()
152 // On some subtargets, 64-bit shift is a quarter rate instruction. In the in tryCombineAll()
219 assert(SrcSize == 16 || SrcSize == 32 || SrcSize == 64); in matchUCharToFloat()
421 if (MRI.getType(Src0) != LLT::scalar(64)) in matchCombine_s_mul_u64()
424 if (KB->getKnownBits(Src1).countMinLeadingZeros() >= 32 && in matchCombine_s_mul_u64()
425 KB->getKnownBits(Src0).countMinLeadingZeros() >= 32) { in matchCombine_s_mul_u64()
430 if (KB->computeNumSignBits(Src1) >= 33 && in matchCombine_s_mul_u64()
[all …]
H A DAMDGPUPreLegalizerCombiner.cpp54 GISelKnownBits &KB, GISelCSEInfo *CSEInfo,
93 GISelKnownBits &KB, GISelCSEInfo *CSEInfo, in AMDGPUPreLegalizerCombinerImpl() argument
96 : Combiner(MF, CInfo, TPC, &KB, CSEInfo), RuleConfig(RuleConfig), STI(STI), in AMDGPUPreLegalizerCombinerImpl()
97 Helper(Observer, B, /*IsPreLegalize*/ true, &KB, MDT, LI), in AMDGPUPreLegalizerCombinerImpl()
123 if (SrcType != LLT::scalar(64)) in matchClampI64ToI16()
182 LLT::scalar(64)); in applyClampI64ToI16()
266 GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF); in runOnMachineFunction() local
279 AMDGPUPreLegalizerCombinerImpl Impl(MF, CInfo, TPC, *KB, CSEInfo, RuleConfig, in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp32 // ~256KB (~64Kwords). Thus only for code run on the emulator! in isLargeFrame()
34 // The arbitrary value of 0xf000 allows frames of up to ~240KB before spill in isLargeFrame()
36 // For frames less than 240KB, it is assumed that there will be less than in isLargeFrame()
37 // 16KB of function arguments. in isLargeFrame()
/freebsd/sys/dev/cesa/
H A Dcesa.h36 * CESA is able to process data only in CESA SRAM, which is quite small (2 kB).
39 * packets and each packet can hold about 1.75 kB of data.
49 * Expected average request size: 1.5 kB (Ethernet MTU)
50 * Packets per average request: (1.5 kB / 1.75 kB) = 1
60 /* Values below are optimized for requests containing about 1.5 kB of data */
69 #define CESA_MAX_FRAGMENTS 64
79 #define CESA_MAX_HMAC_BLOCK_LEN 64

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