Lines Matching +full:64 +full:kb
56 GISelKnownBits &KB, GISelCSEInfo *CSEInfo,
132 GISelKnownBits &KB, GISelCSEInfo *CSEInfo, in AMDGPUPostLegalizerCombinerImpl() argument
135 : Combiner(MF, CInfo, TPC, &KB, CSEInfo), RuleConfig(RuleConfig), STI(STI), in AMDGPUPostLegalizerCombinerImpl()
137 Helper(Observer, B, /*IsPreLegalize*/ false, &KB, MDT, LI), in AMDGPUPostLegalizerCombinerImpl()
152 // On some subtargets, 64-bit shift is a quarter rate instruction. In the in tryCombineAll()
219 assert(SrcSize == 16 || SrcSize == 32 || SrcSize == 64); in matchUCharToFloat()
421 if (MRI.getType(Src0) != LLT::scalar(64)) in matchCombine_s_mul_u64()
424 if (KB->getKnownBits(Src1).countMinLeadingZeros() >= 32 && in matchCombine_s_mul_u64()
425 KB->getKnownBits(Src0).countMinLeadingZeros() >= 32) { in matchCombine_s_mul_u64()
430 if (KB->computeNumSignBits(Src1) >= 33 && in matchCombine_s_mul_u64()
431 KB->computeNumSignBits(Src0) >= 33) { in matchCombine_s_mul_u64()
495 GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF); in runOnMachineFunction() local
503 AMDGPUPostLegalizerCombinerImpl Impl(MF, CInfo, TPC, *KB, /*CSEInfo*/ nullptr, in runOnMachineFunction()