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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMTInstrFormats.td29 class FIELD5<bits<5> Val> {
30 bits<5> Value = Val;
42 bits<5> rt;
43 let Inst{31-26} = 0b010000; // COP0
48 let Inst{5} = sc.Value;
56 bits<5> rt;
57 bits<5> rd;
61 let Inst{31-26} = 0b010000; // COP0
66 let Inst{5} = u;
75 bits<5> rs;
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H A DMipsDSPInstrFormats.td65 class ADDU_QB_FMT<bits<5> op> : DSPInst {
66 bits<5> rd;
67 bits<5> rs;
68 bits<5> rt;
76 let Inst{5-0} = 0b010000;
79 class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
80 bits<5> rd;
81 bits<5> rs;
89 let Inst{5-0} = 0b010000;
93 class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
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H A DMipsEVAInstrFormats.td52 def OPGROUP_COP0_TLB : OPGROUP<0b010000>;
62 bits<5> rt;
63 bits<5> base = addr{20-16};
73 let Inst{5-0} = Operation.Value;
82 let Inst{5-0} = Operation.Value;
H A DMips32r6InstrFormats.td46 def OPGROUP_COP0 : OPGROUP<0b010000>;
77 class OPCODE5<bits<5> Val> {
78 bits<5> Value = Val;
115 def OPCODE6_CLZ : OPCODE6<0b010000>;
122 class FIELD_FMT<bits<5> Val> {
123 bits<5> Value = Val;
128 class FIELD_CMP_COND<bits<5> Val> {
129 bits<5> Value = Val;
149 class FIELD_CMP_FORMAT<bits<5> Val> {
150 bits<5> Value = Val;
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H A DMicroMipsDSPInstrFormats.td25 bits<5> rd;
26 bits<5> rs;
27 bits<5> rt;
37 bits<5> rt;
38 bits<5> rs;
44 let Inst{5-0} = 0b111100;
48 bits<5> rt;
49 bits<5> rs;
57 let Inst{5-0} = 0b111100;
61 bits<5> rd;
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H A DMicroMips32r6InstrFormats.td57 class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
58 bits<5> rs;
63 let Inst{9-5} = rs;
68 bits<5> rt;
69 bits<5> rs;
81 bits<5> rt;
82 bits<5> rs;
93 class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> {
94 bits<5> imm;
99 let Inst{9-5} = imm;
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H A DMicroMipsInstrFormats.td91 let Inst{5-3} = rt;
136 bits<5> rt;
137 bits<5> offset;
142 let Inst{9-5} = rt;
158 bits<5> rd;
164 let Inst{9-5} = rd;
180 bits<5> rs;
181 bits<5> rd;
186 let Inst{9-5} = rd;
201 class JALR_FM_MM16<bits<5> op> {
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H A DMipsInstrFormats.td35 def FrmFI : Format<5>;
106 let TSFlags{5} = hasForbiddenSlot;
155 bits<5> rd;
156 bits<5> rs;
157 bits<5> rt;
158 bits<5> shamt;
168 let Inst{5-0} = funct;
188 class MFC3OP_FM<bits<6> op, bits<5> mfmt, bits<3> guest> : StdArch {
189 bits<5> rt;
190 bits<5> rd;
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H A DMipsInstrInfo.td768 let PredicateMethod = "isScaledUImm<5, 2>";
775 : ConstantUImmAsmOperandClass<5, [ConstantUImm5_Range2_64AsmOperandClass],
778 : ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus33AsmOperandClass]> {
784 5, [ConstantUImm5ReportUImm6AsmOperandClass], 32>;
786 : ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus32AsmOperandClass], 32> {
789 let RenderMethod = "addConstantUImmOperands<5, 32, -32>";
793 5, [ConstantUImm5Plus32NormalizeAsmOperandClass], 1>{
798 5, [ConstantUImm5Plus1ReportUImm6AsmOperandClass], 1>;
800 : ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus1AsmOperandClass]>;
802 : ConstantSImmAsmOperandClass<5, [ConstantUImm5AsmOperandClass]>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoV.td60 def simm5 : RISCVSImmLeafOp<5> {
64 return isInt<5>(Imm);
76 [{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> {
82 return (isInt<5>(Imm) && Imm != -16) || Imm == 16;
88 [{return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);}]>;
530 class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
618 multiclass VALU_MV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
723 multiclass VSQR_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
728 multiclass VRCP_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
758 multiclass VCLS_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
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/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DResourceManager.h156 /// C | 0b010000 | 0b010000 | 0b000000
334 // C | 0b10010 | 0b10000 | 5
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8-ss-conn.dtsi38 conn_subsys: bus@5b000000 {
44 usbotg1: usb@5b0d0000 {
59 usbmisc1: usbmisc@5b0d0200 {
65 usbphy1: usbphy@5b100000 {
73 usdhc1: mmc@5b010000 {
84 usdhc2: mmc@5b020000 {
97 usdhc3: mmc@5b030000 {
108 fec1: ethernet@5b040000 {
128 fec2: ethernet@5b050000 {
148 usbotg3: usb@5b110000 {
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td208 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
217 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
224 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
234 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
239 class F3R_np<bits<5> opc, string OpcStr> :
749 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
1013 def KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>;
1273 def : Pat<(mul GRRegs:$src, 5),
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.td128 let ParserMatchClass = ShiftAmtImmAsmOperand<5>;
353 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
629 defm LD : LoadA<"ld", 0b000000, 0b010000, load, IntRegs, i32>;
688 // Section B.5 - Store Floating-point Instructions, p. 97
830 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
1135 let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
1136 def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrFormats.td27 def DPSoRegRegFrm : Format<5>;
90 class AddrMode<bits<5> val> {
91 bits<5> Value = val;
98 def AddrMode5 : AddrMode<5>;
135 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
327 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
328 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
329 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
330 // 64 64 - <imm> is encoded in imm6<5:0>
437 let TSFlags{6-5} = IndexModeBits;
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrInfo.td16 let Inst{13-5} = 0b000000100;
27 let Inst{13-5} = 0b000000110;
36 let Inst{13-5} = 0b000000101;
48 let Inst{7-5} = 0b000;
64 let Inst{7-5} = 0b011;
76 let Inst{7-5} = 0b010;
88 let Inst{7-5} = 0b001;
100 let Inst{7-5} = 0b000;
112 let Inst{7-5} = 0b111;
125 let Inst{7-5}
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8195.dtsi610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
647 "vdosys0-4", "vdosys0-5";
1653 bits = <0 5>;
1657 bits = <5 5>;
1665 bits = <0 5>;
1669 bits = <5 5>;
1677 bits = <0 5>;
1681 bits = <5 5>;
1685 bits = <2 5>;
1689 bits = <7 5>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DSVEInstrFormats.td363 bits<5> pattern;
370 let Inst{9-5} = pattern;
741 let Inst{23-22} = opc{5-4};
772 let Inst{23-22} = opc{5-4};
778 let Inst{8-5} = Pn;
797 class sve_int_pfirst_next<bits<2> sz8_64, bits<5> opc, string asm,
811 let Inst{8-5} = Pg;
822 multiclass sve_int_pfirst<bits<5> opc, string asm, SDPatternOperator op> {
828 multiclass sve_int_pnext<bits<5> opc, string asm, SDPatternOperator op> {
844 class sve_int_count_r<bits<2> sz8_64, bits<5> opc, string asm,
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H A DAArch64SVEInstrInfo.td117 def SDT_AArch64_SCATTER_SV : SDTypeProfile<0, 5, [
122 def SDT_AArch64_SCATTER_VS : SDTypeProfile<0, 5, [
951 defm PTEST_PP : sve_int_ptest<0b010000, "ptest", AArch64ptest, AArch64ptest_any>;
1847 def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 5))),
1880 def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 5))),
2559 let AddedComplexity = 5 in {
2590 let AddedComplexity = 5 in {
2606 let Predicates = [HasSVEorSME, UseScalarIncVL], AddedComplexity = 5 in {
3604 …defm SQSHL_ZPmZ : sve2_int_arith_pred<0b010000, "sqshl", int_aarch64_sve_sqshl, "SQSHL_ZPZZ",…
/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h80 …ad and config sync fifo push overflow 1 - RX header sync fifo push overflow 5:2 - RX data sync fif…
81 …3838UL //Access:R DataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop …
108 … (0x1<<5) // VGA palette snoo…
109 …CIEIP_REG_PCIEEP_CMD_VPS_E5_SHIFT 5
155 …_PCI_TYPE_VGA_PALETTE_SNOOP_K2 (0x1<<5) // VGA Palette Snoo…
156 …CIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_K2_SHIFT 5
200 …_SNOOP_BB (0x1<<5) // Does not apply t…
201 …CIEIP_REG_STATUS_COMMAND_VGA_SNOOP_BB_SHIFT 5
643 … (0xff<<0) // The 8-bit MSI Capability ID is set to 5 to indicate that the…
706 …S_E5 (0x1<<5) // Extended tag fie…
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