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/linux/lib/crypto/
H A Dblake2s-generic.c20 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
21 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
22 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
23 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
24 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
25 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
26 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
27 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
28 { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 },
29 { 10, 2, 8, 4, 7, 6, 1, 5, 15, 11, 9, 14, 3, 12, 13, 0 },
[all …]
/linux/drivers/media/platform/verisilicon/
H A Drockchip_vpu2_hw_h264_dec.c28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
36 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
37 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
39 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
40 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
[all …]
H A Dhantro_g1_regs.h41 #define G1_REG_CONFIG_PRIORITY_MODE(x) (((x) & 0x7) << 5)
44 #define G1_REG_CONFIG_DEC_SCMD_DIS BIT(5)
79 #define G1_REG_DEC_CTRL1_TOPFIELDFIRST_E BIT(5)
114 #define G1_REG_DEC_CTRL2_CR_AC_VLCTABLE BIT(5)
125 #define G1_REG_DEC_CTRL2_ALPHA_OFFSET(x) (((x) & 0x1f) << 5)
156 #define G1_REG_DEC_CTRL4_VC1_ADV_E BIT(5)
169 #define G1_REG_DEC_CTRL4_VP7_VERSION BIT(5)
210 #define G1_REG_FWD_PIC_PINIT_RLIST_F1(x) (((x) & 0x1f) << 5)
223 #define G1_REG_DEC_CTRL7_PINIT_RLIST_F11(x) (((x) & 0x1f) << 5)
264 #define G1_REG_BD_REF_PIC_BINIT_RLIST_B0(x) (((x) & 0x1f) << 5)
[all …]
/linux/Documentation/hwmon/
H A Ddme1737.rst66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
70 Fan[3-6] and pwm[3,5-6] are optional features and their availability depends on
75 fan[4-6] and pwm[5-6] don't exist.
94 in0: +5VTR (+5V standby) 0V - 6.64V
95 in1: Vccp (processor core) 0V - 3V
96 in2: VCC (internal +3.3V) 0V - 4.38V
97 in3: +5V 0V - 6.64V
98 in4: +12V 0V - 16V
99 in5: VTR (+3.3V standby) 0V - 4.38V
100 in6: Vbat (+3.0V) 0V - 4.38V
[all …]
H A Dltc4245.rst52 in1_input 12v input voltage (mV)
53 in2_input 5v input voltage (mV)
54 in3_input 3v input voltage (mV)
55 in4_input Vee (-12v) input voltage (mV)
57 in1_min_alarm 12v input undervoltage alarm
58 in2_min_alarm 5v input undervoltage alarm
59 in3_min_alarm 3v input undervoltage alarm
60 in4_min_alarm Vee (-12v) input undervoltage alarm
62 curr1_input 12v current (mA)
63 curr2_input 5v current (mA)
[all …]
H A Dcorsair-psu.rst51 curr2_input Current on the 12v psu rail
52 curr2_crit Current max critical value on the 12v psu rail
53 curr3_input Current on the 5v psu rail
54 curr3_crit Current max critical value on the 5v psu rail
55 curr4_input Current on the 3.3v psu rail
56 curr4_crit Current max critical value on the 3.3v psu rail
59 in1_input Voltage of the 12v psu rail
60 in1_crit Voltage max critical value on the 12v psu rail
61 in1_lcrit Voltage min critical value on the 12v psu rail
62 in2_input Voltage of the 5v psu rail
[all …]
H A Dmc13783-adc.rst47 0 Battery Voltage (BATT) 2.50 - 4.65V -2.40V
49 2 Application Supply (BP) 2.50 - 4.65V -2.40V
50 3 Charger Voltage (CHRGRAW) 0 - 10V / /5
51 0 - 20V /10
52 4 Charger Current (CHRGISNSP-CHRGISNSN) -0.25 - 0.25V x4
53 5 General Purpose ADIN5 / Battery Pack Thermistor 0 - 2.30V No
54 6 General Purpose ADIN6 / Backup Voltage (LICELL) 0 - 2.30V / No /
55 1.50 - 3.50V -1.20V
56 7 General Purpose ADIN7 / UID / Die Temperature 0 - 2.30V / No /
57 0 - 2.55V / x0.9 / No
[all …]
/linux/arch/arm/crypto/
H A Dblake2b-neon-core.S53 .byte 3, 4, 5, 6, 7, 0, 1, 2
55 .byte 2, 3, 4, 5, 6, 7, 0, 1
63 // Execute one round of BLAKE2b by updating the state matrix v[0..15] in the
73 // (v[0], v[4], v[8], v[12]), (v[1], v[5], v[9], v[13]),
74 // (v[2], v[6], v[10], v[14]), and (v[3], v[7], v[11], v[15]).
145 // (v[0], v[5], v[10], v[15]), (v[1], v[6], v[11], v[12]),
146 // (v[2], v[7], v[8], v[13]), and (v[3], v[4], v[9], v[14]).
245 .align 5
274 // 'v'. Fortunately, there are exactly enough NEON registers to fit the
285 veor q6, q6, q14 // v[12..13] = IV[4..5] ^ t[0..1]
[all …]
/linux/drivers/iio/dac/
H A Dad3552r.h16 #define AD3552R_MASK_ADDR_ASCENSION BIT(5)
44 #define AD3552R_MASK_STRICT_REGISTER_ACCESS BIT(5)
47 #define AD3552R_MASK_CLOCK_COUNTING_ERROR BIT(5)
60 #define AD3552R_MASK_SAMPLE_HOLD_DIFF_USER_EN BIT(5)
66 #define AD3552R_MASK_CLOCK_COUNT_ERR_ALARM BIT(5)
74 #define AD3552R_MASK_STREAM_EXCEEDS_DAC_ERR_STATUS BIT(5)
90 #define AD3552R_MASK_CH_GAIN_SCALING_N GENMASK(6, 5)
133 #define AD3552R_MAX_RANGES 5
134 #define AD3542R_MAX_RANGES 5
189 /* Internal source with Vref I/O at 2.5V */
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-packed-hsv.rst14 The *saturation* (s) and the *value* (v) are measured in percentage of the
47 - 5
56 - 5
65 - 5
74 - 5
96 - h\ :sub:`5`
105 - s\ :sub:`5`
112 - v\ :sub:`7`
113 - v\ :sub:`6`
114 - v\ :sub:`5`
[all …]
/linux/drivers/gpu/drm/exynos/
H A Dregs-scaler.h60 * 5 b0 b4 b8 bc 190 194 198 19c
74 * 5 118 11c 1f8 1fc
168 #define SCALER_INT_EN_ILLEGAL_SRC_Y_SPAN (1 << 5)
196 #define SCALER_INT_STATUS_ILLEGAL_SRC_Y_SPAN (1 << 5)
205 #define SCALER_SRC_CFG_GET_BYTE_SWAP(r) SCALER_GET(r, 6, 5)
206 #define SCALER_SRC_CFG_SET_BYTE_SWAP(v) SCALER_SET(v, 6, 5) argument
208 #define SCALER_SRC_CFG_SET_COLOR_FORMAT(v) SCALER_SET(v, 4, 0) argument
213 #define SCALER_ARGB1555 5
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16) argument
234 #define SCALER_SRC_SPAN_SET_Y_SPAN(v) SCALER_SET(v, 13, 0) argument
[all …]
/linux/Documentation/devicetree/bindings/iio/dac/
H A Dadi,ltc2664.yaml14 Analog Devices LTC2664 4 channel, 12-/16-Bit, +-10V DAC
31 v-pos-supply:
34 v-neg-supply:
61 0 - MPS2=GND, MPS1=GND, MSP0=GND (+-10V, reset to 0V)
62 1 - MPS2=GND, MPS1=GND, MSP0=VCC (+-5V, reset to 0V)
63 2 - MPS2=GND, MPS1=VCC, MSP0=GND (+-2.5V, reset to 0V)
64 3 - MPS2=GND, MPS1=VCC, MSP0=VCC (0V to 10, reset to 0V)
65 4 - MPS2=VCC, MPS1=GND, MSP0=GND (0V to 10V, reset to 5V)
66 5 - MPS2=VCC, MPS1=GND, MSP0=VCC (0V to 5V, reset to 0V)
67 6 - MPS2=VCC, MPS1=VCC, MSP0=GND (0V to 5V, reset to 2.5V)
[all …]
/linux/tools/testing/selftests/rseq/
H A Drseq-arm-bits.h14 int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int c… in RSEQ_TEMPLATE_IDENTIFIER()
29 "ldr r0, %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
35 "ldr r0, %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
40 "str %[newv], %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
42 RSEQ_INJECT_ASM(5) in RSEQ_TEMPLATE_IDENTIFIER()
43 "b 5f\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
45 "5:\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
50 [v] "m" (*v), in RSEQ_TEMPLATE_IDENTIFIER()
81 int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpnev_storeoffp_load)(intptr_t *v, intptr_t expectnot, in RSEQ_TEMPLATE_IDENTIFIER()
97 "ldr r0, %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
[all …]
H A Drseq-mips-bits.h14 int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int c… in RSEQ_TEMPLATE_IDENTIFIER()
29 LONG_L " $4, %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
34 LONG_L " $4, %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
38 LONG_S " %[newv], %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
40 RSEQ_INJECT_ASM(5) in RSEQ_TEMPLATE_IDENTIFIER()
41 "b 5f\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
43 "5:\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
48 [v] "m" (*v), in RSEQ_TEMPLATE_IDENTIFIER()
74 int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpnev_storeoffp_load)(intptr_t *v, intptr_t expectnot, in RSEQ_TEMPLATE_IDENTIFIER()
90 LONG_L " $4, %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
[all …]
/linux/drivers/media/platform/sunxi/sun6i-csi/
H A Dsun6i_csi_reg.h18 #define SUN6I_CSI_EN_PTN_CYCLE(v) (((v) << 16) & GENMASK(23, 16)) argument
29 #define SUN6I_CSI_IF_CFG_FIELD_DT_PCLK_SHIFT(v) (((v) << 24) & GENMASK(27, 24)) argument
54 #define SUN6I_CSI_IF_CFG_IF_CSI_BT1120 (5 << 0)
57 #define SUN6I_CSI_CAP_MASK(v) (((v) << 2) & GENMASK(5, 2)) argument
70 #define SUN6I_CSI_CH_CFG_PAD_VAL(v) (((v) << 24) & GENMASK(31, 24)) argument
71 #define SUN6I_CSI_CH_CFG_INPUT_FMT(v) (((v) << 20) & GENMASK(23, 20)) argument
72 #define SUN6I_CSI_CH_CFG_OUTPUT_FMT(v) (((v) << 16) & GENMASK(19, 16)) argument
78 #define SUN6I_CSI_CH_CFG_INPUT_YUV_SEQ(v) (((v) << 8) & GENMASK(9, 8)) argument
91 #define SUN6I_CSI_OUTPUT_FMT_FRAME_RGB888 5
106 #define SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420SP 5
[all …]
/linux/tools/testing/selftests/net/forwarding/
H A Drouter_multicast.sh5 # | H1 (v$h1) |
24 # | H2 (v$h2) | | | H3 (v$h3) | |
44 ip route add 198.51.100.16/28 vrf v$h1 nexthop via 198.51.100.1
45 ip route add 198.51.100.32/28 vrf v$h1 nexthop via 198.51.100.1
47 ip route add 2001:db8:2::/64 vrf v$h1 nexthop via 2001:db8:1::1
48 ip route add 2001:db8:3::/64 vrf v$h1 nexthop via 2001:db8:1::1
57 ip route del 2001:db8:3::/64 vrf v$h1
58 ip route del 2001:db8:2::/64 vrf v$h1
60 ip route del 198.51.100.32/28 vrf v$h1
61 ip route del 198.51.100.16/28 vrf v$h1
[all …]
/linux/drivers/staging/media/sunxi/sun6i-isp/
H A Dsun6i_isp_reg.h21 #define SUN6I_ISP_FE_CFG_SRC0_MODE(v) (((v) << 8) & GENMASK(9, 8)) argument
22 #define SUN6I_ISP_FE_CFG_SRC1_MODE(v) (((v) << 16) & GENMASK(17, 16)) argument
30 #define SUN6I_ISP_FE_CTRL_GAMMA_UPDATE BIT(5)
33 #define SUN6I_ISP_FE_CTRL_OUTPUT_SPEED_CTRL(v) (((v) << 16) & GENMASK(17, 16)) argument
42 #define SUN6I_ISP_FE_INT_EN_SRC1_FIFO BIT(5)
53 #define SUN6I_ISP_FE_INT_STA_SRC1_FIFO BIT(5)
104 #define SUN6I_ISP_MODE_INPUT_FMT(v) ((v) & GENMASK(2, 0)) argument
105 #define SUN6I_ISP_MODE_INPUT_YUV_SEQ(v) (((v) << 3) & GENMASK(4, 3)) argument
106 #define SUN6I_ISP_MODE_OTF_DPC(v) (((v) << 16) & BIT(16)) argument
107 #define SUN6I_ISP_MODE_SHARP(v) (((v) << 17) & BIT(17)) argument
[all …]
/linux/drivers/comedi/drivers/
H A Ddt2815.c23 * 0 == unipolar 5V (0V -- +5V)
24 * 1 == bipolar 5V (-5V -- +5V)
29 * 0 == program 1 (see manual table 5-4)
30 * 1 == program 2 (see manual table 5-4)
31 * 2 == program 3 (see manual table 5-4)
32 * 3 == program 4 (see manual table 5-4)
33 * [5] - Analog output 0 range configuration
40 * [10] - Analog output 5 range configuration (same options)
119 * 0 == unipolar 5V (0V -- +5V)
120 * 1 == bipolar 5V (-5V -- +5V)
[all …]
H A Dicp_multi.c24 * 12-bit resolution. Ranges : 5V, 10V, +/-5V, +/-10V, 0..20mA and 4..20mA.
28 * There are 4 x 12-bit Analogue Outputs. Ranges : 5V, 10V, +/-5V, +/-10V
30 * 16 x Digital Inputs, 24V
32 * 8 x Digital Outputs, 24V, 1A
45 #define ICP_MULTI_ADC_CSR_RA BIT(5) /* Input range 0 = 5V, 1 = 10V */
54 #define ICP_MULTI_DAC_CSR_RA BIT(5) /* Output range 0 = 5V, 1 = 10V */
66 #define ICP_MULTI_INT_CIE1 BIT(5) /* Counter 1 overrun interrupt */
78 UNI_RANGE(5),
80 BIP_RANGE(5),
220 /* Reset the analog output channels to 0V */ in icp_multi_reset()
[all …]
/linux/sound/soc/codecs/
H A Dcs43130.h47 #define CS43130_PLL_SET_5 0x030005 /* PLL Setting 5 */
121 #define CS43130_INT_STATUS_5 0x0F0004 /* Interrupt Status 5 */
126 #define CS43130_INT_MASK_5 0x0F0014 /* Interrupt Mask 5 */
141 #define CS43130_HP_DETECT_INV_SHIFT 5
147 #define CS43130_HP_UNPLUG_INT_SHIFT 5
225 #define CS43130_PDN_DSDIF_SHIFT 5
304 #define CS43130_DSD_SRC_SHIFT 5
379 struct u16_fract v; member
384 { 22579200, 32000, .v = { 10, 441, }, },
385 { 22579200, 44100, .v = { 1, 32, }, },
[all …]
/linux/include/linux/platform_data/
H A Dad5761.h13 * @AD5761_VOLTAGE_RANGE_M10V_10V: -10V to 10V
14 * @AD5761_VOLTAGE_RANGE_0V_10V: 0V to 10V
15 * @AD5761_VOLTAGE_RANGE_M5V_5V: -5V to 5V
16 * @AD5761_VOLTAGE_RANGE_0V_5V: 0V to 5V
17 * @AD5761_VOLTAGE_RANGE_M2V5_7V5: -2.5V to 7.5V
18 * @AD5761_VOLTAGE_RANGE_M3V_3V: -3V to 3V
19 * @AD5761_VOLTAGE_RANGE_0V_16V: 0V to 16V
20 * @AD5761_VOLTAGE_RANGE_0V_20V: 0V to 20V
/linux/arch/alpha/kernel/
H A Dentry.S64 stq $5, 40($sp)
82 .cfi_rel_offset $5, 40
106 ldq $5, 40($sp)
131 .cfi_restore $5
261 stq $5, 40($sp)
289 .cfi_rel_offset $5, 5*8
320 ldq $5, 40($sp)
348 .cfi_restore $5
454 lda $5, sys_call_table
459 s8addq $0, $5, $5
[all …]
/linux/drivers/rtc/
H A Drtc-da9052.c22 #define DA9052_GET_TIME_RETRIES 5
59 uint8_t v[2][5]; in da9052_read_alarm() local
63 ret = da9052_group_read(rtc->da9052, DA9052_ALARM_MI_REG, 5, &v[0][0]); in da9052_read_alarm()
71 DA9052_ALARM_MI_REG, 5, &v[idx][0]); in da9052_read_alarm()
77 if (memcmp(&v[0][0], &v[1][0], 5) == 0) { in da9052_read_alarm()
78 rtc_tm->tm_year = (v[0][4] & DA9052_RTC_YEAR) + 100; in da9052_read_alarm()
79 rtc_tm->tm_mon = (v[0][3] & DA9052_RTC_MONTH) - 1; in da9052_read_alarm()
80 rtc_tm->tm_mday = v[0][2] & DA9052_RTC_DAY; in da9052_read_alarm()
81 rtc_tm->tm_hour = v[0][1] & DA9052_RTC_HOUR; in da9052_read_alarm()
82 rtc_tm->tm_min = v[0][0] & DA9052_RTC_MIN; in da9052_read_alarm()
[all …]
/linux/drivers/staging/media/sunxi/cedrus/
H A Dcedrus_regs.h13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
105 ((v) ? BIT(7) : 0)
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
107 ((v) ? BIT(6) : 0)
108 #define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \ argument
109 ((v) ? BIT(5) : 0)
110 #define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \ argument
111 ((v) ? BIT(4) : 0)
[all …]
/linux/drivers/video/fbdev/
H A Dhitfb.c110 hitfb_writew((1 << 5) | 1, HD64461_BBTMDR); in hitfb_accel_bitblt()
117 hitfb_writew((1 << 5), HD64461_BBTMDR); in hitfb_accel_bitblt()
188 unsigned short v; in hitfb_blank() local
191 v = hitfb_readw(HD64461_LDR1); in hitfb_blank()
192 v &= ~HD64461_LDR1_DON; in hitfb_blank()
193 hitfb_writew(v, HD64461_LDR1); in hitfb_blank()
195 v = hitfb_readw(HD64461_LCDCCR); in hitfb_blank()
196 v |= HD64461_LCDCCR_MOFF; in hitfb_blank()
197 hitfb_writew(v, HD64461_LCDCCR); in hitfb_blank()
199 v = hitfb_readw(HD64461_STBCR); in hitfb_blank()
[all …]

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