Lines Matching +full:5 +full:v
47 #define CS43130_PLL_SET_5 0x030005 /* PLL Setting 5 */
121 #define CS43130_INT_STATUS_5 0x0F0004 /* Interrupt Status 5 */
126 #define CS43130_INT_MASK_5 0x0F0014 /* Interrupt Mask 5 */
141 #define CS43130_HP_DETECT_INV_SHIFT 5
147 #define CS43130_HP_UNPLUG_INT_SHIFT 5
225 #define CS43130_PDN_DSDIF_SHIFT 5
304 #define CS43130_DSD_SRC_SHIFT 5
379 struct u16_fract v; member
384 { 22579200, 32000, .v = { 10, 441, }, },
385 { 22579200, 44100, .v = { 1, 32, }, },
386 { 22579200, 48000, .v = { 5, 147, }, },
387 { 22579200, 88200, .v = { 1, 16, }, },
388 { 22579200, 96000, .v = { 10, 147, }, },
389 { 22579200, 176400, .v = { 1, 8, }, },
390 { 22579200, 192000, .v = { 20, 147, }, },
391 { 22579200, 352800, .v = { 1, 4, }, },
392 { 22579200, 384000, .v = { 40, 147, }, },
393 { 24576000, 32000, .v = { 1, 48, }, },
394 { 24576000, 44100, .v = { 147, 5120, }, },
395 { 24576000, 48000, .v = { 1, 32, }, },
396 { 24576000, 88200, .v = { 147, 2560, }, },
397 { 24576000, 96000, .v = { 1, 16, }, },
398 { 24576000, 176400, .v = { 147, 1280, }, },
399 { 24576000, 192000, .v = { 1, 8, }, },
400 { 24576000, 352800, .v = { 147, 640, }, },
401 { 24576000, 384000, .v = { 1, 4, }, },
406 { 22579200, 32000, .v = { 20, 441, }, },
407 { 22579200, 44100, .v = { 1, 16, }, },
408 { 22579200, 48000, .v = { 10, 147, }, },
409 { 22579200, 88200, .v = { 1, 8, }, },
410 { 22579200, 96000, .v = { 20, 147, }, },
411 { 22579200, 176400, .v = { 1, 4, }, },
412 { 22579200, 192000, .v = { 40, 147, }, },
413 { 22579200, 352800, .v = { 1, 2, }, },
414 { 22579200, 384000, .v = { 80, 147, }, },
415 { 24576000, 32000, .v = { 1, 24, }, },
416 { 24576000, 44100, .v = { 147, 2560, }, },
417 { 24576000, 48000, .v = { 1, 16, }, },
418 { 24576000, 88200, .v = { 147, 1280, }, },
419 { 24576000, 96000, .v = { 1, 8, }, },
420 { 24576000, 176400, .v = { 147, 640, }, },
421 { 24576000, 192000, .v = { 1, 4, }, },
422 { 24576000, 352800, .v = { 147, 320, }, },
423 { 24576000, 384000, .v = { 1, 2, }, },
428 { 22579200, 32000, .v = { 100, 147, }, },
429 { 22579200, 44100, .v = { 3, 32, }, },
430 { 22579200, 48000, .v = { 5, 49, }, },
431 { 22579200, 88200, .v = { 3, 16, }, },
432 { 22579200, 96000, .v = { 10, 49, }, },
433 { 22579200, 176400, .v = { 3, 8, }, },
434 { 22579200, 192000, .v = { 20, 49, }, },
435 { 22579200, 352800, .v = { 3, 4, }, },
436 { 22579200, 384000, .v = { 40, 49, }, },
437 { 24576000, 32000, .v = { 1, 16, }, },
438 { 24576000, 44100, .v = { 441, 5120, }, },
439 { 24576000, 48000, .v = { 3, 32, }, },
440 { 24576000, 88200, .v = { 441, 2560, }, },
441 { 24576000, 96000, .v = { 3, 16, }, },
442 { 24576000, 176400, .v = { 441, 1280, }, },
443 { 24576000, 192000, .v = { 3, 8, }, },
444 { 24576000, 352800, .v = { 441, 640, }, },
445 { 24576000, 384000, .v = { 3, 4, }, },
450 { 22579200, 32000, .v = { 40, 441, }, },
451 { 22579200, 44100, .v = { 1, 8, }, },
452 { 22579200, 48000, .v = { 20, 147, }, },
453 { 22579200, 88200, .v = { 1, 4, }, },
454 { 22579200, 96000, .v = { 40, 147, }, },
455 { 22579200, 176400, .v = { 1, 2, }, },
456 { 22579200, 192000, .v = { 80, 147, }, },
457 { 22579200, 352800, .v = { 1, 1, }, },
458 { 24576000, 32000, .v = { 1, 12, }, },
459 { 24576000, 44100, .v = { 147, 1280, }, },
460 { 24576000, 48000, .v = { 1, 8, }, },
461 { 24576000, 88200, .v = { 147, 640, }, },
462 { 24576000, 96000, .v = { 1, 4, }, },
463 { 24576000, 176400, .v = { 147, 320, }, },
464 { 24576000, 192000, .v = { 1, 2, }, },
465 { 24576000, 352800, .v = { 147, 160, }, },
466 { 24576000, 384000, .v = { 1, 1, }, },
485 #define CS43130_NUM_SUPPLIES 5
494 #define CS43130_NUM_INT 5 /* number of interrupt status reg */