Searched +full:5 +full:p49v5923 (Results 1 – 2 of 2) sorted by relevance
| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | idt,versaclock5.yaml | 7 title: IDT VersaClock 5 and 6 programmable I2C clock generators
10 The IDT VersaClock 5 and VersaClock 6 are programmable I2C
16 - 5P49V5923:
21 - 5P49V5933:
53 - idt,5p49v5923
54 - idt,5p49v5925
55 - idt,5p49v5933
56 - idt,5p49v5935
57 - idt,5p49v60
58 - idt,5p49v6901
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| /linux/drivers/clk/ |
| H A D | clk-versaclock5.c | 3 * Driver for IDT Versaclock 5
95 #define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5
123 #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5)
133 #define VC5_MAX_CLK_OUT_NUM 5
436 u8 fb[5]; in vc5_pll_recalc_rate()
438 regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); in vc5_pll_recalc_rate()
478 u8 fb[5]; in vc5_pll_set_rate()
486 return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); in vc5_pll_set_rate()
820 * After getting feedback from Renesas, the .5pF steps were the in vc5_map_cap_value()
828 * The Programmer's guide shows XTAL[5:0] but in reality, in vc5_map_cap_value()
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