Lines Matching +full:5 +full:p49v5923
3 * Driver for IDT Versaclock 5
95 #define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5
123 #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5)
133 #define VC5_MAX_CLK_OUT_NUM 5
436 u8 fb[5]; in vc5_pll_recalc_rate()
438 regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); in vc5_pll_recalc_rate()
478 u8 fb[5]; in vc5_pll_set_rate()
486 return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5); in vc5_pll_set_rate()
820 * After getting feedback from Renesas, the .5pF steps were the in vc5_map_cap_value()
828 * The Programmer's guide shows XTAL[5:0] but in reality, in vc5_map_cap_value()
1251 .clk_out_cnt = 5,
1267 .clk_out_cnt = 5,
1275 .clk_out_cnt = 5,
1283 .clk_out_cnt = 5,
1291 .clk_out_cnt = 5,
1299 .clk_out_cnt = 5,
1305 { "5p49v5923", .driver_data = (kernel_ulong_t)&idt_5p49v5923_info },
1306 { "5p49v5925", .driver_data = (kernel_ulong_t)&idt_5p49v5925_info },
1307 { "5p49v5933", .driver_data = (kernel_ulong_t)&idt_5p49v5933_info },
1308 { "5p49v5935", .driver_data = (kernel_ulong_t)&idt_5p49v5935_info },
1309 { "5p49v60", .driver_data = (kernel_ulong_t)&idt_5p49v60_info },
1310 { "5p49v6901", .driver_data = (kernel_ulong_t)&idt_5p49v6901_info },
1311 { "5p49v6965", .driver_data = (kernel_ulong_t)&idt_5p49v6965_info },
1312 { "5p49v6975", .driver_data = (kernel_ulong_t)&idt_5p49v6975_info },
1318 { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
1319 { .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info },
1320 { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
1321 { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
1322 { .compatible = "idt,5p49v60", .data = &idt_5p49v60_info },
1323 { .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
1324 { .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info },
1325 { .compatible = "idt,5p49v6975", .data = &idt_5p49v6975_info },
1345 MODULE_DESCRIPTION("IDT VersaClock 5 driver");