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/freebsd/share/man/man4/
H A Dahc.447 .Xr loader.conf 5 :
89 .Bl -column "aic7895CX" "MIPSX" "PCI/64X" "MaxSyncX" "MaxWidthX" "SCBsX" "2 3 4 5 6 7 8X"
91 .It "aic7770" Ta "10" Ta "VL" Ta "10MHz" Ta "16Bit" Ta "4" Ta "1"
92 .It "aic7850" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "8Bit" Ta "3" Ta ""
93 .It "aic7860" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "8Bit" Ta "3" Ta ""
94 .It "aic7870" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "16Bit" Ta "16" Ta ""
95 .It "aic7880" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta ""
96 .It "aic7890" Ta "20" Ta "PCI/32" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
97 .It "aic7891" Ta "20" Ta "PCI/64" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
98 .It "aic7892" Ta "20" Ta "PCI/64" Ta "80MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
[all …]
H A Diwlwifi.440 .Xr rc.conf 5 .
44 .Xr rc.conf 5
87 .\" awk -F\\t '{ print $5 }' ~/tmp/iwlwifi_pci_ids_name.txt | \
149 Killer (R) Wireless-AC 1550 Wireless Network Adapter (9260NGW) 160MHz
155 Killer(R) Wireless-AC 1550s Wireless Network Adapter (9560D2W) 160MHz
157 Killer(R) Wireless-AC 1550i Wireless Network Adapter (9560NGW) 160MHz
159 Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)
161 Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)
165 Intel(R) Wi-Fi 6 AX200 160MHz
167 Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)
[all …]
/freebsd/contrib/wpa/src/common/
H A Dieee802_11_common.c52 if (elen < 5) { in ieee802_11_parse_vendor_specific()
512 if (elen != 5) in __ieee802_11_parse_elems()
1013 if (sub_elem_len < 5) { in ieee802_11_parse_link_assoc_req()
1016 "MLD: error: sub_elem_len=%zu < 5", in ieee802_11_parse_link_assoc_req()
1311 pos[4] >= '0' && pos[4] <= '9' && pos[5] == '_') { in hostapd_config_tx_queue()
1375 * @freq: Frequency (MHz) to convert
1395 if ((freq - 2407) % 5) in ieee80211_freq_to_channel_ext()
1409 *channel = (freq - 2407) / 5; in ieee80211_freq_to_channel_ext()
1425 if ((freq - 4000) % 5) in ieee80211_freq_to_channel_ext()
1427 *channel = (freq - 4000) / 5; in ieee80211_freq_to_channel_ext()
[all …]
H A Dhw_features_common.c138 "HT40: control channel: %d (%d MHz), secondary channel: %d (%d MHz)", in allowed_ht40_channel_pair()
141 /* Verify that HT40 secondary channel is an allowed 20 MHz in allowed_ht40_channel_pair()
153 * IEEE 802.11n Annex J. This is only needed for 5 GHz band since in allowed_ht40_channel_pair()
291 wpa_printf(MSG_DEBUG, "Found overlapping 20 MHz HT BSS: " in check_20mhz_bss()
316 wpa_printf(MSG_DEBUG, "40 MHz affected channel range: [%d,%d] MHz", in check_40mhz_2g4()
324 /* Check for overlapping 20 MHz BSS */ in check_40mhz_2g4()
328 "Overlapping 20 MHz BSS is found"); in check_40mhz_2g4()
352 "40 MHz pri/sec mismatch with BSS " in check_40mhz_2g4()
373 "40 MHz Intolerant is set on channel %d in BSS " in check_40mhz_2g4()
449 /* TODO: 320 MHz */ in punct_update_legacy_bw()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos5433-tmu.dtsi42 atlas0_alert_5: atlas0-alert-5 {
56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
74 /* Set maximum frequency as 1500MHz */
76 cooling-device = <&cpu4 4 5>, <&cpu5 4 5>,
77 <&cpu6 4 5>, <&cpu7 4 5>;
80 /* Set maximum frequency as 1400MHz */
82 cooling-device = <&cpu4 5 7>, <&cpu5 5 7>,
83 <&cpu6 5 7>, <&cpu7 5 7>;
[all …]
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drs.h14 * bandwidths <= 80MHz
16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
146 * <nss, channel-width> pair (0 - 80mhz widt
[all...]
H A Dmac.h36 * @MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
47 #define MAC_FLG_SHORT_PREAMBLE BIT(5)
150 COEX_HIGH_PRIORITY_ENABLE = BIT(5),
442 #define MAX_CHANNEL_BW_INDX_API_D_VER_2 5
449 * (0=SISO, 1=MIMO2) x (0-20MHz, 1-40MHz, 2-80MHz, 3-160MHz)
451 * 0=BPSK, 1=QPSK, 2=16QAM, 3=64QAM, 4=256QAM, 5=1024QAM, 6=RES, 7=NONE
457 * For each Nss/Bw define 2 QAM thrsholds (0..5)
[all...]
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3288-veyron-mickey.dts21 vcc_5v: vcc-5v {
86 * and don't let the GPU go faster than 400 MHz.
106 * - 800 MHz (hot)
107 * - 800 MHz - 696 MHz (hotter)
108 * - 696 MHz - min (very hot)
111 * - 800 MHz appears to be a "sweet spot" for me. I can run
113 * - After 696 MHz we stop lowering voltage, so throttling
118 cooling-device = <&cpu0 5 6>, <&cpu1 5 6>, <&cpu2 5 6>,
119 <&cpu3 5 6>;
139 /* At very hot, don't let GPU go over 300 MHz */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmicrel.txt14 KSZ8021: register 0x1f, bits 5..4
15 KSZ8031: register 0x1f, bits 5..4
16 KSZ8051: register 0x1f, bits 5..4
17 KSZ8081: register 0x1f, bits 5..4
18 KSZ8091: register 0x1f, bits 5..4
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c131 PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz)
132 PLLU: Clock source for USB PHY, provides 12/60/480 MHz
136 PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum)
154 { 5, 4},
155 { 6, 5},
174 { 8, 5},
185 { 5, 4},
186 { 6, 5},
210 {5, 4},
211 {6, 5},
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Darmada3700-periph-clock.txt20 5 setm_tmx Serial Embedded Trace Module
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
H A Dsamsung,exynosautov9-clock.yaml20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
48 maxItems: 5
52 maxItems: 5
71 - description: External reference clock (26 MHz)
87 - description: External reference clock (26 MHz)
105 - description: External reference clock (26 MHz)
123 - description: External reference clock (26 MHz)
141 - description: External reference clock (26 MHz)
161 - description: External reference clock (26 MHz)
183 - description: External reference clock (26 MHz)
[all …]
H A Dsamsung,exynos850-clock.yaml20 two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
50 maxItems: 5
54 maxItems: 5
73 - description: External reference clock (26 MHz)
89 - description: External reference clock (26 MHz)
107 - description: External reference clock (26 MHz)
125 - description: External reference clock (26 MHz)
143 - description: External reference clock (26 MHz)
167 - description: External reference clock (26 MHz)
187 - description: External reference clock (26 MHz)
[all …]
H A Dgoogle,gs101-clock.yaml16 is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
40 maxItems: 5
44 maxItems: 5
71 - description: External reference clock (24.576 MHz)
87 - description: External reference clock (24.576 MHz)
112 - description: External reference clock (24.576 MHz)
156 - description: External reference clock (24.576 MHz)
/freebsd/contrib/wpa/src/ap/
H A Dacs.c52 * - Ideal channel may end up overlapping a channel with 40 MHz intolerant BSS
64 * - include neighboring BSS scan to avoid conflicts with 40 MHz intolerant BSSs
103 * 10^(chan_nf/5) + (busy time - tx time) / (active time - tx time) *
121 * overlap with 20 MHz bandwidth, but there is no overlap for 20 MHz bandwidth
122 * on 5 GHz.
135 * ACS: Survey analysis for channel 1 (2412 MHz)
139 * ACS: 4: min_nf=-113 interference_factor=0.0310559 nf=-113 time=161 busy=0 rx=5
140 * ACS: 5: min_nf=-113 interference_factor=0.0248447 nf=-113 time=161 busy=0 rx=4
142 * ACS: Survey analysis for channel 2 (2417 MHz)
147 * ACS: 5: min_nf=-113 interference_factor=0.0248447 nf=-113 time=161 busy=0 rx=4
[all …]
H A Dieee802_11_ht.c71 host_to_le16(5); in hostapd_eid_ht_capabilities()
115 - all STAs in the BSS are 20/40 MHz HT in 20/40 MHz BSS or
116 - all STAs in the BSS are 20 MHz HT in 20 MHz BSS
120 however and at least one 20 MHz HT STA is associated
183 int pri = 2407 + 5 * channel; in is_40_allowed()
200 wpa_printf(MSG_ERROR, "40 MHz affected channel range: [%d,%d] MHz", in is_40_allowed()
229 "Ignore 20/40 BSS Coexistence Management frame since 40 MHz capability is not enabled"); in hostapd_2040_coex_action()
263 (bc_ie->coex_param & (BIT(5) | BIT(6) | BIT(7))) ? in hostapd_2040_coex_action()
267 /* Intra-BSS communication prohibiting 20/40 MHz BSS operation in hostapd_2040_coex_action()
279 "20 MHz BSS width request bit is set in BSS coexistence information field"); in hostapd_2040_coex_action()
[all …]
/freebsd/contrib/tcpdump/
H A Dprint-802_11.c242 #define E_TIM 5
403 ND_PRINT("%s%2.1f%s", _sep, (.5 * ((_r) & 0x7f)), _suf)
430 * 0 for 20 MHz, 1 for 40 MHz;
436 { /* 20 Mhz */ { 6.5f, /* SGI */ 7.2f, },
437 /* 40 Mhz */ { 13.5f, /* SGI */ 15.0f, },
441 { /* 20 Mhz */ { 13.0f, /* SGI */ 14.4f, },
442 /* 40 Mhz */ { 27.0f, /* SGI */ 30.0f, },
446 { /* 20 Mhz */ { 19.5f, /* SGI */ 21.7f, },
447 /* 40 Mhz */ { 40.5f, /* SGI */ 45.0f, },
451 { /* 20 Mhz */ { 26.0f, /* SGI */ 28.9f, },
[all …]
/freebsd/sys/contrib/device-tree/Bindings/input/touchscreen/
H A Dstmpe.txt19 5 -> 5 ms
27 4 -> 5 ms
28 5 -> 10 ms
44 5 -> 96 clocks
53 0 -> 1.625 MHz
54 1 -> 3.25 MHz
55 2 || 3 -> 6.5 MHz
78 /* 3.25 MHz ADC clock speed */
92 /* 5 ms touch detect interrupt delay */
93 st,touch-det-delay = <5>;
/freebsd/contrib/wpa/wpa_supplicant/
H A DREADME-NAN-USD29 …ice_name=<name> [ttl=<time-to-live-in-sec>] [freq=<in MHz>] [freq_list=<comma separate list of MHz…
34 If freq is not included, the default frequency 2437 MHz (channel 6 on
39 channel list automatically based on the list of allowed 2.4 and 5 GHz
59 NAN_SUBSCRIBE service_name=<name> [active=1] [ttl=<time-to-live-in-sec>] [freq=<in MHz>] [srv_proto…
64 If freq is not included, the default frequency 2437 MHz (channel 6 on
117 --> returns 5
121 event on dev0: <3>NAN-DISCOVERY-RESULT subscribe_id=7 publish_id=5 address=02:00:00:00:01:00 fsd=1 …
126 event on dev1: <3>NAN-RECEIVE id=5 peer_instance_id=7 address=02:00:00:00:00:00 ssi=
130 dev0: NAN_TRANSMIT handle=7 req_instance_id=5 address=02:00:00:00:01:00 ssi=8899
134 event on dev1: <3>NAN-RECEIVE id=5 peer_instance_id=7 address=02:00:00:00:00:00 ssi=8899
[all …]
/freebsd/sys/contrib/device-tree/Bindings/input/
H A Diqs626a.yaml60 enum: [0, 1, 2, 3, 4, 5, 6, 7]
70 5: 135
84 enum: [0, 1, 2, 3, 4, 5, 6, 7]
94 5: Generic channel 1
271 1: 5 uA
283 0: 4 MHz (1 MHz)
284 1: 2 MHz (500 kHz)
285 2: 1 MHz (250 kHz)
397 0: 16 MHz (4 MHz)
398 1: 8 MHz (2 MHz)
[all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c96 #define PLLM_IDDQ_BIT 5
189 .i_width = 5, \
253 { 5, 4},
254 { 6, 5},
270 /* PLLM: 880 MHz Clock source for EMC 2x clock */
280 .mnp_bits = {8, 8, 5, 0, 8, 20},
282 /* PLLMB: 880 MHz Clock source for EMC 2x clock */
292 .mnp_bits = {8, 8, 5, 0, 8, 20},
304 .mnp_bits = {8, 8, 5, 0, 8, 20},
306 /* PLLC: 510 MHz Clock source for camera use */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar9002/
H A Dar9280.c54 * Take the MHz channel value and set the Channel value
62 * (freq_ref = 40MHz)
64 * For 5GHz channel,
66 * (freq_ref = 40MHz/(24>>amodeRefSel))
68 * For 5GHz channels which are 5MHz spaced,
70 * (freq_ref = 40MHz)
134 /* Enable 2G (fractional) mode for channels which are 5MHz spaced */ in ar9280SetChannel()
137 * Workaround for talking on PSB non-5MHz channels; in ar9280SetChannel()
138 * the pre-Merlin chips only had a 2.5MHz channel in ar9280SetChannel()
146 * resolution in this reference is 2.5MHz) and thus in ar9280SetChannel()
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmedia5200.dts29 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
30 bus-frequency = <132000000>; // 132 MHz
31 clock-frequency = <396000000>; // 396 MHz
40 bus-frequency = <132000000>;// 132 MHz
87 0xc000 0 0 4 &media5200_fpga 0 5
91 0xc800 0 0 3 &media5200_fpga 0 5
95 0xd000 0 0 2 &media5200_fpga 0 5
97 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dmaxim,max8952.yaml42 enum: [0, 1, 2, 3, 4, 5, 6, 7]
51 - 5: 1mV/us
62 - 0: 26 MHz
63 - 1: 13 MHz
64 - 2: 19.2 MHz
65 Defaults to 26 MHz if not specified.
/freebsd/sys/contrib/dev/iwlwifi/mvm/
H A Drfi.c11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
42 /* frequency 4267MHz */
47 /* frequency 4400MHz */
52 /* frequency 5200MHz */
57 /* frequency 5600MHz */
[all...]

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