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/linux/Documentation/devicetree/bindings/phy/
H A Dapm,xgene-phy.yaml7 title: APM X-Gene 15Gbps Multi-purpose PHY
13 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
146 0 = 1-2Gbps
147 1 = 2-4Gbps (1st tuple default)
148 2 = 4-8Gbps
149 3 = 8-15Gbps (2nd tuple default)
150 4 = 2.5-4Gbps
151 5 = 4-5Gbps
152 6 = 5-6Gbps
153 7 = 6-16Gbps (3rd tuple default).
/linux/drivers/scsi/mvsas/
H A Dmv_94xx.h75 /* ports 5-7 follow after this */
81 /* ports 5-7 follow after this */
87 /* ports 5-7 follow after this */
146 MVS_IRQ_COM_OUT_I2O_HOS1 = (1 << 5),
180 * bit 2: 6Gbps support
181 * bit 1: 3Gbps support
182 * bit 0: 1.5Gbps support
188 * bit 5: G1 (1.5Gbps) Without SSC
189 * bit 4: G1 (1.5Gbps) with SSC
190 * bit 3: G2 (3.0Gbps) Without SSC
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_arcturus.h61 #define FEATURE_DPM_MP0CLK_BIT 5
192 #define THROTTLER_TEMP_VR_MEM_BIT 5
217 #define WORKLOAD_PPLIB_COUNT 5
429 XGMI_LINK_RATE_2 = 2, // 2Gbps
430 XGMI_LINK_RATE_4 = 4, // 4Gbps
431 XGMI_LINK_RATE_8 = 8, // 8Gbps
432 XGMI_LINK_RATE_12 = 12, // 12Gbps
433 XGMI_LINK_RATE_16 = 16, // 16Gbps
434 XGMI_LINK_RATE_17 = 17, // 17Gbps
435 XGMI_LINK_RATE_18 = 18, // 18Gbps
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h81 #define FEATURE_DPM_SOCCLK_BIT 5
200 #define THROTTLER_TEMP_VR_MEM0_BIT 5
224 #define FW_DSTATE_MP1_DS_BIT 5
453 #define NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS 5
524 XGMI_LINK_RATE_2 = 2, // 2Gbps
525 XGMI_LINK_RATE_4 = 4, // 4Gbps
526 XGMI_LINK_RATE_8 = 8, // 8Gbps
527 XGMI_LINK_RATE_12 = 12, // 12Gbps
528 XGMI_LINK_RATE_16 = 16, // 16Gbps
529 XGMI_LINK_RATE_17 = 17, // 17Gbps
[all …]
H A Dsmu13_driver_if_aldebaran.h43 #define FEATURE_DPM_LCLK_BIT 5
116 #define THROTTLER_SPARE_5 5
358 uint8_t XgmiLinkSpeed[NUM_XGMI_DPM_LEVELS]; //Gbps [EX: 32 = 32Gbps]
552 #define TABLE_DRIVER_SMU_CONFIG 5
/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
71 #define CFG_0_RX_FC_EN_SHIFT 5
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
129 #define CFG_3_CF_DROP_SHIFT 5
/linux/tools/testing/selftests/drivers/net/hw/
H A Ddevlink_rate_tc_bw.py39 - Total bandwidth: 1Gbps
132 cmd(f"tc qdisc add dev {vf_ifc} root handle 5 mqprio mode dcb hw 1 num_tc 8")
216 {"index": 5, "bw": 0},
280 gbps = bits_per_second / 1e9
281 if gbps < min_expected_gbps:
283 f"iperf3 bandwidth too low: {gbps:.2f} Gbps "
284 f"(expected ≥ {min_expected_gbps} Gbps)"
287 return gbps
372 f"Total bandwidth {total:.2f} Gbps < minimum "
373 f"{validator.total_min_expected:.2f} Gbps; "
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmicrochip,sparx5-switch.yaml15 The SparX-5 Enterprise Ethernet switch family provides a rich set of
29 The SparX-5 switch family targets managed Layer 2 and Layer 3
31 1G/2.5G/5G/10G switching with 10G/25G aggregation links is required.
137 the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
138 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
146 the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
147 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
/linux/drivers/net/phy/
H A Dphy-core.c31 return "1Gbps"; in phy_speed_to_str()
33 return "2.5Gbps"; in phy_speed_to_str()
35 return "5Gbps"; in phy_speed_to_str()
37 return "10Gbps"; in phy_speed_to_str()
39 return "14Gbps"; in phy_speed_to_str()
41 return "20Gbps"; in phy_speed_to_str()
43 return "25Gbps"; in phy_speed_to_str()
45 return "40Gbps"; in phy_speed_to_str()
47 return "50Gbps"; in phy_speed_to_str()
49 return "56Gbps"; in phy_speed_to_str()
[all …]
/linux/tools/testing/selftests/drivers/net/mlxsw/
H A Dqos_lib.sh29 # 1Gbps. That wouldn't saturate egress and MC would thus get through,
30 # seemingly winning bandwidth on account of UC. Demand at least 2Gbps
34 for i in {5..0}; do
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dmaxim,max96717.yaml25 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
27 MAX96717F only supports a fixed rate of 3Gbps in the forward direction.
73 maxItems: 5
H A Dmaxim,max96714.yaml23 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
25 MAX96714F only supports a fixed rate of 3Gbps in the forward direction.
76 maxItems: 5
/linux/include/rdma/
H A Dopa_port_info.h32 #define OPA_LINKDOWN_REASON_BAD_SLID 5
96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
97 #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
98 #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
108 #define OPA_CAP_MASK3_IsAddrRangeConfigSupported (1 << 5)
164 OPA_PI_MASK_PORT_LINK_ENABLED = (0x001F << 5),
181 OPA_PI_MASK_INTERLEAVE_MAX_NEST_TX = (0x001F << 5),
225 OPA_PI_MASK_VL_STALL = (0x03 << 5),
259 u8 cap; /* 3 res, 5 bits */
270 u8 smsl; /* 3 res, 5 bits */
[all …]
/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_main.h115 #define HCLGE_PHY_MDIX_CTRL_S 5
116 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)
153 #define HCLGE_RESET_INT_M GENMASK(7, 5)
159 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5
170 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U
193 #define HCLGE_SUPPORT_40G_BIT BIT(5)
247 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
248 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
249 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
250 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c432 return 5; in intel_c10_get_tx_vboost_lvl()
436 return 5; in intel_c10_get_tx_vboost_lvl()
446 return 5; in intel_c10_get_tx_term_ctl()
541 .pll[5] = 0x0C,
567 .pll[5] = 0x10,
593 .pll[5] = 0x12,
619 .pll[5] = 0x0A,
645 .pll[5] = 0x0C,
671 .pll[5] = 0x10,
697 .pll[5] = 0x0A,
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-puzzle-m801.dts108 /* SFP+ port 2: 10 Gbps indicator */
115 /* SFP+ port 2: 1 Gbps indicator */
122 /* SFP+ port 1: 10 Gbps indicator */
128 led-5 {
129 /* SFP+ port 1: 1 Gbps indicator */
131 function-enumerator = <5>;
/linux/drivers/usb/host/
H A Dxhci-hub.c26 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
27 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
28 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
29 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
30 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
31 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
32 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
33 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
170 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */ in xhci_create_usb3x_bos_desc()
187 * is 20Gbps, but the BOS descriptor lane speed mantissa is in xhci_create_usb3x_bos_desc()
[all …]
/linux/drivers/net/phy/realtek/
H A Drealtek_main.c76 #define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5)
90 #define RTL8211F_LEDCR_SHIFT 5
116 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0)
121 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0)
138 #define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4)
511 __phy_write(dev, RTL8211F_PHYSICAL_ADDR_WORD2, mac_addr[5] << 8 | (mac_addr[4])); in rtl8211f_set_wol()
1814 .name = "RTL8226 2.5Gbps PHY",
1825 .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
1837 .name = "RTL8226-CG 2.5Gbps PHY",
1847 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
[all …]
/linux/fs/smb/client/
H A Dcifs_debug.c182 return "1Gbps"; in smb_speed_to_str()
184 return "2.5Gbps"; in smb_speed_to_str()
186 return "5Gbps"; in smb_speed_to_str()
188 return "10Gbps"; in smb_speed_to_str()
190 return "14Gbps"; in smb_speed_to_str()
192 return "20Gbps"; in smb_speed_to_str()
194 return "25Gbps"; in smb_speed_to_str()
196 return "40Gbps"; in smb_speed_to_str()
198 return "50Gbps"; in smb_speed_to_str()
200 return "56Gbps"; in smb_speed_to_str()
[all …]
/linux/drivers/usb/gadget/
H A Dconfig.c114 * pointer dereference if a 5gbps capable gadget is used with in usb_assign_descriptors()
115 * a 10gbps capable config (device port + cable + host port) in usb_assign_descriptors()
/linux/drivers/net/ethernet/intel/igc/
H A Digc_mac.c331 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); in igc_rar_set()
489 * Page Ability Register (Address 5) to determine how in igc_config_fc_after_link_up()
502 * Page Ability Register (Address 5) determine flow control in igc_config_fc_after_link_up()
678 /* For I225, STATUS will indicate 1G speed in both 1 Gbps in igc_get_speed_and_duplex_copper()
679 * and 2.5 Gbps link modes. An additional bit is used in igc_get_speed_and_duplex_copper()
680 * to differentiate between 1 Gbps and 2.5 Gbps. in igc_get_speed_and_duplex_copper()
796 * left-shifts where the MSB of mc_addr[5] would still fall within in igc_hash_mc_addr()
801 * number of bits to shift mc_addr[5] left, while still keeping the in igc_hash_mc_addr()
808 * [0] [1] [2] [3] [4] [5] in igc_hash_mc_addr()
813 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 in igc_hash_mc_addr()
[all …]
/linux/drivers/net/ethernet/ibm/ehea/
H A Dehea_phyp.h78 #define H_QPCB0_ALL EHEA_BMASK_IBM(0, 5)
84 #define H_QPCB0_QP_TENURE EHEA_BMASK_IBM(5, 5)
115 #define H_QPCB1_SGEL_NB_RQ1 EHEA_BMASK_IBM(5, 5)
162 #define H_PORT_CB5 5
190 #define H_SPEED_1G_F 6 /* 1 Gbps, Full Duplex */
191 #define H_SPEED_10G_F 8 /* 10 Gbps, Full Duplex */
254 /* Hcall Query/Modify Port Control Block 5 Selection Mask Bits */
/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c61 #define COMPHY_MODE_MASK GENMASK(7, 5)
131 #define CFG_TX_ALIGN_POS_MASK GENMASK(8, 5)
152 #define MODE_REFDIV_MASK GENMASK(5, 4)
163 #define PLL_READY_DLY_MASK GENMASK(7, 5)
300 /* 0 1 2 3 4 5 6 7 */
577 /* 5. Set vendor-specific configuration (It is done in sata driver) */ in mvebu_a3700_comphy_sata_power_on()
608 * All PHY register values are defined in full for 3.125Gbps in comphy_gbe_phy_init()
609 * SERDES speed. The values required for 1.25 Gbps are almost in comphy_gbe_phy_init()
611 * comparison to 3.125 Gbps values. These register values are in comphy_gbe_phy_init()
656 * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY in mvebu_a3700_comphy_ethernet_power_on()
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dmicrochip,usb5744.yaml15 controller, so 5 Gbps SuperSpeed data transfers are not affected by slower
/linux/drivers/scsi/isci/
H A Dinit.c102 static u16 stp_max_occ_to = 5;
106 static u16 ssp_inactive_to = 5;
110 static u16 stp_inactive_to = 5;
116 MODULE_PARM_DESC(phy_gen, "PHY generation (1: 1.5Gbps 2: 3.0Gbps 3: 6.0Gbps)");
470 user->stp_inactivity_timeout = 5; in sci_oem_defaults()
471 user->ssp_inactivity_timeout = 5; in sci_oem_defaults()
472 user->stp_max_occupancy_timeout = 5; in sci_oem_defaults()

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