Home
last modified time | relevance | path

Searched +full:5 +full:gbps (Results 1 – 25 of 119) sorted by relevance

12345

/linux/Documentation/devicetree/bindings/phy/
H A Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
48 0 = 1-2Gbps
49 1 = 2-4Gbps (1st tuple default)
50 2 = 4-8Gbps
51 3 = 8-15Gbps (2nd tuple default)
52 4 = 2.5-4Gbps
53 5 = 4-5Gbps
54 6 = 5-6Gbps
55 7 = 6-16Gbps (3rd tuple default)
/linux/drivers/scsi/mvsas/
H A Dmv_94xx.h75 /* ports 5-7 follow after this */
81 /* ports 5-7 follow after this */
87 /* ports 5-7 follow after this */
146 MVS_IRQ_COM_OUT_I2O_HOS1 = (1 << 5),
180 * bit 2: 6Gbps support
181 * bit 1: 3Gbps support
182 * bit 0: 1.5Gbps support
188 * bit 5: G1 (1.5Gbps) Without SSC
189 * bit 4: G1 (1.5Gbps) with SSC
190 * bit 3: G2 (3.0Gbps) Without SSC
[all …]
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dp_types.h50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane
55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane
57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane
58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane
62 LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_arcturus.h61 #define FEATURE_DPM_MP0CLK_BIT 5
192 #define THROTTLER_TEMP_VR_MEM_BIT 5
217 #define WORKLOAD_PPLIB_COUNT 5
429 XGMI_LINK_RATE_2 = 2, // 2Gbps
430 XGMI_LINK_RATE_4 = 4, // 4Gbps
431 XGMI_LINK_RATE_8 = 8, // 8Gbps
432 XGMI_LINK_RATE_12 = 12, // 12Gbps
433 XGMI_LINK_RATE_16 = 16, // 16Gbps
434 XGMI_LINK_RATE_17 = 17, // 17Gbps
435 XGMI_LINK_RATE_18 = 18, // 18Gbps
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h81 #define FEATURE_DPM_SOCCLK_BIT 5
200 #define THROTTLER_TEMP_VR_MEM0_BIT 5
224 #define FW_DSTATE_MP1_DS_BIT 5
453 #define NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS 5
524 XGMI_LINK_RATE_2 = 2, // 2Gbps
525 XGMI_LINK_RATE_4 = 4, // 4Gbps
526 XGMI_LINK_RATE_8 = 8, // 8Gbps
527 XGMI_LINK_RATE_12 = 12, // 12Gbps
528 XGMI_LINK_RATE_16 = 16, // 16Gbps
529 XGMI_LINK_RATE_17 = 17, // 17Gbps
[all …]
H A Dsmu13_driver_if_aldebaran.h43 #define FEATURE_DPM_LCLK_BIT 5
116 #define THROTTLER_SPARE_5 5
358 uint8_t XgmiLinkSpeed[NUM_XGMI_DPM_LEVELS]; //Gbps [EX: 32 = 32Gbps]
552 #define TABLE_DRIVER_SMU_CONFIG 5
/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
71 #define CFG_0_RX_FC_EN_SHIFT 5
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
129 #define CFG_3_CF_DROP_SHIFT 5
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dmaxim,max96717.yaml25 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
27 MAX96717F only supports a fixed rate of 3Gbps in the forward direction.
73 maxItems: 5
H A Dmaxim,max96714.yaml23 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
25 MAX96714F only supports a fixed rate of 3Gbps in the forward direction.
76 maxItems: 5
/linux/tools/testing/selftests/drivers/net/mlxsw/
H A Dqos_lib.sh29 # 1Gbps. That wouldn't saturate egress and MC would thus get through,
30 # seemingly winning bandwidth on account of UC. Demand at least 2Gbps
34 for i in {5..0}; do
/linux/include/rdma/
H A Dopa_port_info.h32 #define OPA_LINKDOWN_REASON_BAD_SLID 5
96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
97 #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
98 #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
108 #define OPA_CAP_MASK3_IsAddrRangeConfigSupported (1 << 5)
164 OPA_PI_MASK_PORT_LINK_ENABLED = (0x001F << 5),
181 OPA_PI_MASK_INTERLEAVE_MAX_NEST_TX = (0x001F << 5),
225 OPA_PI_MASK_VL_STALL = (0x03 << 5),
259 u8 cap; /* 3 res, 5 bits */
270 u8 smsl; /* 3 res, 5 bits */
[all …]
/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_main.h115 #define HCLGE_PHY_MDIX_CTRL_S 5
116 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)
153 #define HCLGE_RESET_INT_M GENMASK(7, 5)
159 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5
170 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U
193 #define HCLGE_SUPPORT_40G_BIT BIT(5)
247 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
248 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
249 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
250 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c424 return 5; in intel_c10_get_tx_vboost_lvl()
428 return 5; in intel_c10_get_tx_vboost_lvl()
438 return 5; in intel_c10_get_tx_term_ctl()
533 .pll[5] = 0x0C,
559 .pll[5] = 0x10,
585 .pll[5] = 0x12,
611 .pll[5] = 0x0A,
637 .pll[5] = 0x0C,
663 .pll[5] = 0x10,
689 .pll[5] = 0x0A,
[all …]
/linux/drivers/usb/host/
H A Dxhci-hub.c26 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
27 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
28 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
29 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
30 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
31 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
32 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
33 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
170 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */ in xhci_create_usb3x_bos_desc()
187 * is 20Gbps, but the BOS descriptor lane speed mantissa is in xhci_create_usb3x_bos_desc()
[all …]
/linux/Documentation/networking/device_drivers/ethernet/pensando/
H A Dionic.rst36 ionic 0000:b5:00.0 enp181s0: Link up - 100 Gbps
39 ionic 0000:b6:00.0 enp182s0: Link up - 100 Gbps
121 414 5 0 0 0 0
138 rx_packets: 5
201 frames_rx_multicast: 5
/linux/fs/smb/client/
H A Dcifs_debug.c180 return "1Gbps"; in smb_speed_to_str()
182 return "2.5Gbps"; in smb_speed_to_str()
184 return "5Gbps"; in smb_speed_to_str()
186 return "10Gbps"; in smb_speed_to_str()
188 return "14Gbps"; in smb_speed_to_str()
190 return "20Gbps"; in smb_speed_to_str()
192 return "25Gbps"; in smb_speed_to_str()
194 return "40Gbps"; in smb_speed_to_str()
196 return "50Gbps"; in smb_speed_to_str()
198 return "56Gbps"; in smb_speed_to_str()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_capability.c147 case 0x08: // 5 lttpr repeaters in dp_parse_lttpr_repeater_count()
148 return 5; in dp_parse_lttpr_repeater_count()
184 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation. in linkRateInKHzToLinkRateMultiplier()
187 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
190 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
193 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
196 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
199 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2)- 3.24 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
202 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
205 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2)- 5.40 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
[all …]
/linux/drivers/net/ethernet/ibm/ehea/
H A Dehea_phyp.h78 #define H_QPCB0_ALL EHEA_BMASK_IBM(0, 5)
84 #define H_QPCB0_QP_TENURE EHEA_BMASK_IBM(5, 5)
115 #define H_QPCB1_SGEL_NB_RQ1 EHEA_BMASK_IBM(5, 5)
162 #define H_PORT_CB5 5
190 #define H_SPEED_1G_F 6 /* 1 Gbps, Full Duplex */
191 #define H_SPEED_10G_F 8 /* 10 Gbps, Full Duplex */
254 /* Hcall Query/Modify Port Control Block 5 Selection Mask Bits */
/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c61 #define COMPHY_MODE_MASK GENMASK(7, 5)
131 #define CFG_TX_ALIGN_POS_MASK GENMASK(8, 5)
152 #define MODE_REFDIV_MASK GENMASK(5, 4)
163 #define PLL_READY_DLY_MASK GENMASK(7, 5)
300 /* 0 1 2 3 4 5 6 7 */
577 /* 5. Set vendor-specific configuration (It is done in sata driver) */ in mvebu_a3700_comphy_sata_power_on()
608 * All PHY register values are defined in full for 3.125Gbps in comphy_gbe_phy_init()
609 * SERDES speed. The values required for 1.25 Gbps are almost in comphy_gbe_phy_init()
611 * comparison to 3.125 Gbps values. These register values are in comphy_gbe_phy_init()
656 * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY in mvebu_a3700_comphy_ethernet_power_on()
[all …]
/linux/Documentation/devicetree/bindings/ata/
H A Dapm-xgene.txt17 5th optional memory resource shall be the host
24 * "sata-phy" for the SATA 6.0Gbps PHY
/linux/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt8195.c35 /* HDMI 2.0 specification, 3.4Gbps <= TMDS Bit Rate <= 6G, in mtk_phy_tmds_clk_ratio()
36 * clock bit ratio 1:40, under 3.4Gbps, clock bit ratio 1:10 in mtk_phy_tmds_clk_ratio()
140 case 5: in mtk_hdmi_pll_set_hw()
252 * ICO clk = 5*TMDS_CLK*TXPOSDIV*TXPREDIV in mtk_hdmi_pll_calc()
253 * ICO clk constraint: 5G =< ICO clk <= 12G in mtk_hdmi_pll_calc()
256 ns_hdmipll_ck = 5 * tmds_clk * txposdiv * txpredivs[i]; in mtk_hdmi_pll_calc()
257 if (ns_hdmipll_ck >= 5 * GIGA && in mtk_hdmi_pll_calc()
262 (ns_hdmipll_ck < 5 * GIGA || ns_hdmipll_ck > 12 * GIGA)) { in mtk_hdmi_pll_calc()
385 usleep_range(5, 10); in mtk_hdmi_pll_prepare()
387 usleep_range(5, 1 in mtk_hdmi_pll_prepare()
[all...]
/linux/Documentation/networking/
H A Dphy.rst249 data rate of 1Gbps. Embedded in the data stream is a 16-bit control
251 remote end. This does not include "up-clocked" variants such as 2.5Gbps
262 encoding. The underlying data rate is 1Gbps, with the slower speeds of
266 receipt. This does not include "up-clocked" variants such as 2.5Gbps
276 This is the IEEE 802.3 Clause 129 defined 5GBASE-R protocol. It is
308 rate of 125Mpbs using a 4B/5B encoding scheme, resulting in an underlying
327 This is the Penta SGMII mode, it is similar to QSGMII but it combines 5
/linux/Documentation/devicetree/bindings/usb/
H A Dmicrochip,usb5744.yaml15 controller, so 5 Gbps SuperSpeed data transfers are not affected by slower
/linux/drivers/scsi/isci/
H A Dinit.c102 u16 stp_max_occ_to = 5;
106 u16 ssp_inactive_to = 5;
110 u16 stp_inactive_to = 5;
116 MODULE_PARM_DESC(phy_gen, "PHY generation (1: 1.5Gbps 2: 3.0Gbps 3: 6.0Gbps)");
470 user->stp_inactivity_timeout = 5; in sci_oem_defaults()
471 user->ssp_inactivity_timeout = 5; in sci_oem_defaults()
472 user->stp_max_occupancy_timeout = 5; in sci_oem_defaults()
/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-board.c114 * ports MII0 = 0, MII1 = 1, SGMII = 2-5. in cvmx_helper_board_get_mii_address()
221 /* The simulator gives you a simulated 1Gbps full duplex link */ in __cvmx_helper_board_link_get()
253 case 2: /* 1 Gbps */ in __cvmx_helper_board_link_get()

12345