| /linux/tools/perf/pmu-events/arch/x86/arrowlake/ |
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
24 "Counter": "0,1,2,3,4,5,6,7",
27 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
34 "Counter": "0,1,2,3,4,5,6,7,8,9",
37 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
44 "Counter": "0,1,2,3,4,5,6,7,8,9",
53 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
|
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
25 "Counter": "0,1,2,3,4,5,6,7",
35 "Counter": "0,1,2,3,4,5,6,7,8,9",
45 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
46 "Counter": "0,1,2,3,4,5,6,7,8,9",
49 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
56 "Counter": "0,1,2,3,4,5,6,7,8,9",
65 "Counter": "0,1,2,3,4,5,6,7",
68 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/lunarlake/ |
| H A D | virtual-memory.json | 3 …"BriefDescription": "Counts the number of page walks initiated by a demand load that missed the fi…
4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
21 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
22 "Counter": "0,1,2,3,4,5,6,7",
31 "Counter": "0,1,2,3,4,5,6,7,8,9",
40 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
41 "Counter": "0,1,2,3,4,5,6,7,8,9",
45 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
52 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
23 "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
24 "Counter": "0,1,2,3,4,5,6,7",
33 "Counter": "0,1,2,3,4,5,6,7",
41 "BriefDescription": "Counts the number of BACLEARS due to a return branch.",
42 "Counter": "0,1,2,3,4,5,6,7",
50 "BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.",
[all …]
|
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
25 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7,8,9",
64 "Counter": "0,1,2,3,4,5,6,7",
73 "Counter": "0,1,2,3,4,5,6,7",
81 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
82 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
|
| H A D | other.json | 3 …re not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and…
4 "Counter": "0,1,2,3,4,5,6,7,8,9",
7 …re not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
22 …"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to a lock In Progr…
23 "Counter": "0,1,2,3,4,5,6,7",
26 …Counts the number of unhalted cycles a Core is blocked due to a lock In Progress issued by another…
32 …"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to an Accepted loc…
33 "Counter": "0,1,2,3,4,5,6,7",
36 …r of unhalted cycles a Core is blocked due to an Accepted lock it issued, includes both split and …
[all …]
|
| /linux/arch/alpha/lib/ |
| H A D | ev6-memset.S | 23 * A future enhancement might be to put in a byte store loop for really
25 * a win in the kernel would depend upon the contextual usage.
41 .align 5
48 * undertake a major re-write to interleave the constant materialization
64 inswl $17,4,$5 # U : 0000chch00000000
69 or $2,$5,$2 # E : chchchch00000000
70 bic $1,7,$1 # E : fit within a single quadword?
79 * Target address is misaligned, and won't fit within a quadword
82 bis $16,$16,$5 # E : Save the address
92 stq_u $1,0($5) # L : Store result
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/pantherlake/ |
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
23 "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
24 "Counter": "0,1,2,3,4,5,6,7",
33 "Counter": "0,1,2,3,4,5,6,7",
41 "BriefDescription": "Counts the number of BACLEARS due to a return branch.",
42 "Counter": "0,1,2,3,4,5,6,7",
50 "BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.",
[all …]
|
| H A D | virtual-memory.json | 3 …"BriefDescription": "Counts the number of page walks initiated by a demand load that missed the fi…
4 "Counter": "0,1,2,3,4,5,6,7",
12 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
13 "Counter": "0,1,2,3,4,5,6,7",
22 "Counter": "0,1,2,3,4,5,6,7,8,9",
31 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
32 "Counter": "0,1,2,3,4,5,6,7,8,9",
36 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
43 "Counter": "0,1,2,3,4,5,6,7",
52 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
[all …]
|
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7,8,9",
15 "Counter": "0,1,2,3,4,5,6,7,8,9",
25 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
26 "Counter": "0,1,2,3,4,5,6,7,8,9",
29 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
36 "Counter": "0,1,2,3,4,5,6,7,8,9",
45 "Counter": "0,1,2,3,4,5,6,7",
48 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
54 "Counter": "0,1,2,3,4,5,6,7,8,9",
63 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 … evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) li…
13 "Counter": "0,1,2,3,4,5,6,7",
16 … of cache lines filled into the L2 cache that are in Exclusive state. Counts on a per core basis.",
22 "Counter": "0,1,2,3,4,5,6,7",
25 …er of cache lines filled into the L2 cache that are in Forward state. Counts on a per core basis.",
31 "Counter": "0,1,2,3,4,5,6,7",
34 …r of cache lines filled into the L2 cache that are in Modified state. Counts on a per core basis.",
40 "Counter": "0,1,2,3,4,5,6,7",
43 …ber of cache lines filled into the L2 cache that are in Shared state. Counts on a per core basis.",
[all …]
|
| /linux/tools/testing/selftests/mm/ |
| H A D | mremap_dontunmap.c | 40 // Try a simple operation for to "test" for kernel support this prevents
97 unsigned long num_pages = 5; in mremap_dontunmap_simple()
104 memset(source_mapping, 'a', num_pages * page_size); in mremap_dontunmap_simple()
113 // the dest_mapping contains a's. in mremap_dontunmap_simple()
115 (dest_mapping, num_pages * page_size, 'a') != 0, in mremap_dontunmap_simple()
128 // This test validates that MREMAP_DONTUNMAP on a shared mapping works as expected.
131 unsigned long num_pages = 5; in mremap_dontunmap_simple_shmem()
146 memset(source_mapping, 'a', num_pages * page_size); in mremap_dontunmap_simple_shmem()
162 // the dest_mapping contains a's. in mremap_dontunmap_simple_shmem()
164 (dest_mapping, num_pages * page_size, 'a') != 0, in mremap_dontunmap_simple_shmem()
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/alderlaken/ |
| H A D | cache.json | 3 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
4 "Counter": "0,1,2,3,4,5",
7 …ejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.",
11 …ription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core bas…
12 "Counter": "0,1,2,3,4,5",
15 …Cache accesses that resulted in a hit from a front door request only (does not include rejects or …
20 …ription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core ba…
21 "Counter": "0,1,2,3,4,5",
24 …Cache accesses that resulted in a miss from a front door request only (does not include rejects or…
29 …"Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
[all …]
|
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5",
13 "Counter": "0,1,2,3,4,5",
21 "Counter": "0,1,2,3,4,5",
29 "Counter": "0,1,2,3,4,5",
38 "Counter": "0,1,2,3,4,5",
46 "Counter": "0,1,2,3,4,5",
54 "Counter": "0,1,2,3,4,5",
57 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
62 "Counter": "0,1,2,3,4,5",
71 "Counter": "0,1,2,3,4,5",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 … evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) li…
13 "Counter": "0,1,2,3,4,5,6,7",
16 … of cache lines filled into the L2 cache that are in Exclusive state. Counts on a per core basis.",
22 "Counter": "0,1,2,3,4,5,6,7",
25 …er of cache lines filled into the L2 cache that are in Forward state. Counts on a per core basis.",
31 "Counter": "0,1,2,3,4,5,6,7",
34 …r of cache lines filled into the L2 cache that are in Modified state. Counts on a per core basis.",
40 "Counter": "0,1,2,3,4,5,6,7",
43 …ber of cache lines filled into the L2 cache that are in Shared state. Counts on a per core basis.",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/alderlake/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
15 "Counter": "0,1,2,3,4,5",
25 "Counter": "0,1,2,3,4,5,6,7",
36 "Counter": "0,1,2,3,4,5",
45 "Counter": "0,1,2,3,4,5",
54 "Counter": "0,1,2,3,4,5,6,7",
65 "Counter": "0,1,2,3,4,5",
75 "Counter": "0,1,2,3,4,5,6,7",
85 "Counter": "0,1,2,3,4,5",
94 "Counter": "0,1,2,3,4,5",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/meteorlake/ |
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 …the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predict…
17 …s resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch whic…
27 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
46 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
53 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
73 "Counter": "0,1,2,3,4,5,6,7",
84 …of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots…
85 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
25 "Counter": "0,1,2,3,4,5,6,7",
34 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
35 "Counter": "0,1,2,3,4,5,6,7",
38 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
45 "Counter": "0,1,2,3,4,5,6,7",
49 … in which the instruction pointer (IP) of the processor is resteered due to a branch instruction a…
55 "Counter": "0,1,2,3,4,5,6,7",
64 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
22 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
23 "Counter": "0,1,2,3,4,5,6,7",
26 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
32 "Counter": "0,1,2,3,4,5,6,7",
40 "Counter": "0,1,2,3,4,5,6,7",
49 "Counter": "0,1,2,3,4,5,6,7",
58 "Counter": "0,1,2,3,4,5,6,7",
67 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
52 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
53 "Counter": "0,1,2,3,4,5,6,7",
56 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
62 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
52 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
53 "Counter": "0,1,2,3,4,5,6,7",
56 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
62 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
22 "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
23 "Counter": "0,1,2,3,4,5,6,7",
26 "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
32 "Counter": "0,1,2,3,4,5,6,7",
40 "Counter": "0,1,2,3,4,5,6,7",
49 "Counter": "0,1,2,3,4,5,6,7",
58 "Counter": "0,1,2,3,4,5,6,7",
67 "Counter": "0,1,2,3,4,5,
50 { global() object
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/icelake/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
22 "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
23 "Counter": "0,1,2,3,4,5,6,7",
26 "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
32 "Counter": "0,1,2,3,4,5,6,7",
40 "Counter": "0,1,2,3,4,5,6,7",
49 "Counter": "0,1,2,3,4,5,6,7",
58 "Counter": "0,1,2,3,4,5,6,7",
67 "Counter": "0,1,2,3,4,5,
50 { global() object
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
22 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
23 "Counter": "0,1,2,3,4,5,6,7",
26 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
32 "Counter": "0,1,2,3,4,5,6,7",
40 "Counter": "0,1,2,3,4,5,6,7",
49 "Counter": "0,1,2,3,4,5,6,7",
58 "Counter": "0,1,2,3,4,5,6,7",
67 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/graniterapids/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
22 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
23 "Counter": "0,1,2,3,4,5,6,7",
26 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
32 "Counter": "0,1,2,3,4,5,6,7",
40 "Counter": "0,1,2,3,4,5,6,7",
49 "Counter": "0,1,2,3,4,5,6,7",
58 "Counter": "0,1,2,3,4,5,6,7",
67 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|