| /linux/tools/perf/pmu-events/arch/x86/arrowlake/ |
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
24 "Counter": "0,1,2,3,4,5,6,7",
27 "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
33 "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
34 "Counter": "0,1,2,3,4,5,
50 { global() object
[all...] |
| H A D | virtual-memory.json | 3 …"BriefDescription": "Counts the number of page walks initiated by a demand load that missed the fi…
4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
21 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
22 "Counter": "0,1,2,3,4,5,6,7",
31 "Counter": "0,1,2,3,4,5,6,7,8,9",
40 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
41 "Counter": "0,1,2,3,4,5,6,7",
49 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
50 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
|
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
25 "Counter": "0,1,2,3,4,5,6,7",
35 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7,8,9",
56 "Counter": "0,1,2,3,4,5,6,7",
65 "Counter": "0,1,2,3,4,5,6,7",
73 "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
74 "Counter": "0,1,2,3,4,5,6,7,8,9",
77 "PublicDescription": "Counts the number of occurrences where a microcod
54 { global() object
[all...] |
| H A D | other.json | 3 …re not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and…
4 "Counter": "0,1,2,3,4,5,6,7,8,9",
7 …re not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
22 …"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to a lock In Progr…
23 "Counter": "0,1,2,3,4,5,6,7",
26 …Counts the number of unhalted cycles a Core is blocked due to a lock In Progress issued by another…
32 …"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to an Accepted loc…
33 "Counter": "0,1,2,3,4,5,6,7",
36 …r of unhalted cycles a Core is blocked due to an Accepted lock it issued, includes both split and …
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/lunarlake/ |
| H A D | virtual-memory.json | 3 …"BriefDescription": "Counts the number of page walks initiated by a demand load that missed the fi…
4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
21 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
22 "Counter": "0,1,2,3,4,5,6,7",
31 "Counter": "0,1,2,3,4,5,6,7,8,9",
40 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
41 "Counter": "0,1,2,3,4,5,6,7,8,9",
45 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
52 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
23 "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
24 "Counter": "0,1,2,3,4,5,6,7",
33 "Counter": "0,1,2,3,4,5,6,7",
41 "BriefDescription": "Counts the number of BACLEARS due to a retur
49 { global() object
[all...] |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
25 "Counter": "0,1,2,3,4,5,6,7",
35 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
55 "Counter": "0,1,2,3,4,5,6,7,8,9",
66 "Counter": "0,1,2,3,4,5,6,7",
75 "Counter": "0,1,2,3,4,5,6,7",
83 "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
84 "Counter": "0,1,2,3,4,5,
53 { global() object
[all...] |
| H A D | other.json | 3 …re not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and…
4 "Counter": "0,1,2,3,4,5,6,7,8,9",
7 …re not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and…
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
22 …"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to a lock In Progr…
23 "Counter": "0,1,2,3,4,5,6,7",
26 …Counts the number of unhalted cycles a Core is blocked due to a lock In Progress issued by another…
32 …"BriefDescription": "Counts the number of unhalted cycles a Core is blocked due to an Accepted loc…
33 "Counter": "0,1,2,3,4,5,6,7",
36 …r of unhalted cycles a Core is blocked due to an Accepted lock it issued, includes both split and …
[all …]
|
| /linux/arch/alpha/lib/ |
| H A D | ev6-memset.S | 23 * A future enhancement might be to put in a byte store loop for really
25 * a win in the kernel would depend upon the contextual usage.
41 .align 5
48 * undertake a major re-write to interleave the constant materialization
64 inswl $17,4,$5 # U : 0000chch00000000
69 or $2,$5,$2 # E : chchchch00000000
70 bic $1,7,$1 # E : fit within a single quadword?
79 * Target address is misaligned, and won't fit within a quadword
82 bis $16,$16,$5 # E : Save the address
92 stq_u $1,0($5) # L : Store result
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/pantherlake/ |
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
23 "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
24 "Counter": "0,1,2,3,4,5,6,7",
33 "Counter": "0,1,2,3,4,5,6,7",
41 "BriefDescription": "Counts the number of BACLEARS due to a retur
49 { global() object
[all...] |
| H A D | virtual-memory.json | 3 "BriefDescription": "Counts the number of page walks initiated by a demand load that missed the first and second level TLBs.",
4 "Counter": "0,1,2,3,4,5,6,7",
12 "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.",
13 "Counter": "0,1,2,3,4,5,6,7",
22 "Counter": "0,1,2,3,4,5,6,7,8,9",
31 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
32 "Counter": "0,1,2,3,4,5,
51 { global() object
[all...] |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
25 "Counter": "0,1,2,3,4,5,6,7",
35 "Counter": "0,1,2,3,4,5,6,7,8,9",
46 "Counter": "0,1,2,3,4,5,6,7",
55 "Counter": "0,1,2,3,4,5,6,7",
63 "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
64 "Counter": "0,1,2,3,4,5,6,7,8,9",
67 "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists.",
74 "Counter": "0,1,2,3,4,5,
52 { global() object
[all...] |
| /linux/tools/testing/selftests/mm/ |
| H A D | mremap_dontunmap.c | 40 // Try a simple operation for to "test" for kernel support this prevents
97 unsigned long num_pages = 5; in mremap_dontunmap_simple()
104 memset(source_mapping, 'a', num_pages * page_size); in mremap_dontunmap_simple()
113 // the dest_mapping contains a's. in mremap_dontunmap_simple()
115 (dest_mapping, num_pages * page_size, 'a') != 0, in mremap_dontunmap_simple()
128 // This test validates that MREMAP_DONTUNMAP on a shared mapping works as expected.
131 unsigned long num_pages = 5; in mremap_dontunmap_simple_shmem()
146 memset(source_mapping, 'a', num_pages * page_size); in mremap_dontunmap_simple_shmem()
162 // the dest_mapping contains a's. in mremap_dontunmap_simple_shmem()
164 (dest_mapping, num_pages * page_size, 'a') != 0, in mremap_dontunmap_simple_shmem()
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 "PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches. Does not count evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back.",
13 "Counter": "0,1,2,3,4,5,6,7",
16 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Exclusive state. Counts on a per core basis.",
22 "Counter": "0,1,2,3,4,5,6,7",
25 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Forward state. Counts on a per core basis.",
31 "Counter": "0,1,2,3,4,5,6,7",
34 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Modified state. Counts on a per core basis.",
40 "Counter": "0,1,2,3,4,5,
47 { global() object
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/alderlaken/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5",
13 "Counter": "0,1,2,3,4,5",
22 "Counter": "0,1,2,3,4,5",
31 "Counter": "0,1,2,3,4,5",
40 "Counter": "0,1,2,3,4,5",
48 "Counter": "0,1,2,3,4,5",
56 "Counter": "0,1,2,3,4,5",
59 "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.",
64 "Counter": "0,1,2,3,4,5",
73 "Counter": "0,1,2,3,4,5",
46 { global() object
[all...] |
| H A D | cache.json | 3 "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
4 "Counter": "0,1,2,3,4,5",
7 "PublicDescription": "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.",
11 "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.",
12 "Counter": "0,1,2,3,4,5",
15 "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis.",
20 "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a mis
46 { global() object
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/alderlake/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
15 "Counter": "0,1,2,3,4,5",
25 "Counter": "0,1,2,3,4,5,6,7",
36 "Counter": "0,1,2,3,4,5",
46 "Counter": "0,1,2,3,4,5",
56 "Counter": "0,1,2,3,4,5,6,7",
67 "Counter": "0,1,2,3,4,5",
77 "Counter": "0,1,2,3,4,5,6,7",
87 "Counter": "0,1,2,3,4,5",
96 "Counter": "0,1,2,3,4,5",
54 { global() object
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 "PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches. Does not count evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back.",
13 "Counter": "0,1,2,3,4,5,6,7",
16 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Exclusive state. Counts on a per core basis.",
22 "Counter": "0,1,2,3,4,5,6,7",
25 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Forward state. Counts on a per core basis.",
31 "Counter": "0,1,2,3,4,5,6,7",
34 "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Modified state. Counts on a per core basis.",
40 "Counter": "0,1,2,3,4,5,
47 { global() object
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/meteorlake/ |
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
17 "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
27 "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
46 "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transitio
51 { global() object
[all...] |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
25 "Counter": "0,1,2,3,4,5,6,7",
34 "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
35 "Counter": "0,1,2,3,4,5,6,7",
38 "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists.",
45 "Counter": "0,1,2,3,4,5,6,7",
49 "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.",
55 "Counter": "0,1,2,3,4,5,6,7",
64 "Counter": "0,1,2,3,4,5,
53 { global() object
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
22 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
23 "Counter": "0,1,2,3,4,5,6,7",
26 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
32 "Counter": "0,1,2,3,4,5,6,7",
40 "Counter": "0,1,2,3,4,5,6,7",
49 "Counter": "0,1,2,3,4,5,6,7",
58 "Counter": "0,1,2,3,4,5,6,7",
67 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
52 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
53 "Counter": "0,1,2,3,4,5,6,7",
56 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
62 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
24 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
52 … "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
53 "Counter": "0,1,2,3,4,5,6,7",
56 …"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hard…
62 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
22 "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
23 "Counter": "0,1,2,3,4,5,6,7",
26 "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
32 "Counter": "0,1,2,3,4,5,6,7",
40 "Counter": "0,1,2,3,4,5,6,7",
49 "Counter": "0,1,2,3,4,5,6,7",
58 "Counter": "0,1,2,3,4,5,6,7",
67 "Counter": "0,1,2,3,4,5,
50 { global() object
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/icelake/ |
| H A D | pipeline.json | 4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
22 "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
23 "Counter": "0,1,2,3,4,5,6,7",
26 "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
32 "Counter": "0,1,2,3,4,5,6,7",
40 "Counter": "0,1,2,3,4,5,6,7",
49 "Counter": "0,1,2,3,4,5,6,7",
58 "Counter": "0,1,2,3,4,5,6,7",
67 "Counter": "0,1,2,3,4,5,
50 { global() object
[all...] |