1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/qcom,qcm2290-gpucc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Graphics Clock & Reset Controller on QCM2290 8 9maintainers: 10 - Konrad Dybcio <konradybcio@kernel.org> 11 12description: | 13 Qualcomm graphics clock control module provides the clocks, resets and power 14 domains on Qualcomm SoCs. 15 16 See also: 17 include/dt-bindings/clock/qcom,qcm2290-gpucc.h 18 19properties: 20 compatible: 21 enum: 22 - qcom,qcm2290-gpucc 23 - qcom,shikra-gpucc 24 25 reg: 26 maxItems: 1 27 28 clocks: 29 items: 30 - description: AHB interface clock, 31 - description: SoC CXO clock 32 - description: GPLL0 main branch source 33 - description: GPLL0 div branch source 34 35 power-domains: 36 description: 37 A phandle and PM domain specifier for the CX power domain. 38 maxItems: 1 39 40 required-opps: 41 description: 42 A phandle to an OPP node describing required CX performance point. 43 maxItems: 1 44 45required: 46 - compatible 47 - clocks 48 - power-domains 49 50allOf: 51 - $ref: qcom,gcc.yaml# 52 53unevaluatedProperties: false 54 55examples: 56 - | 57 #include <dt-bindings/clock/qcom,gcc-qcm2290.h> 58 #include <dt-bindings/clock/qcom,rpmcc.h> 59 #include <dt-bindings/power/qcom-rpmpd.h> 60 61 soc { 62 #address-cells = <2>; 63 #size-cells = <2>; 64 65 clock-controller@5990000 { 66 compatible = "qcom,qcm2290-gpucc"; 67 reg = <0x0 0x05990000 0x0 0x9000>; 68 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 69 <&rpmcc RPM_SMD_XO_CLK_SRC>, 70 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 71 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 72 power-domains = <&rpmpd QCM2290_VDDCX>; 73 required-opps = <&rpmpd_opp_low_svs>; 74 #clock-cells = <1>; 75 #reset-cells = <1>; 76 #power-domain-cells = <1>; 77 }; 78 }; 79... 80