1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2019-2021 NXP 4 * Zhou Guoniu <guoniu.zhou@nxp.com> 5 */ 6img_ipg_clk: clock-img-ipg { 7 compatible = "fixed-clock"; 8 #clock-cells = <0>; 9 clock-frequency = <200000000>; 10 clock-output-names = "img_ipg_clk"; 11}; 12 13img_pxl_clk: clock-img-pxl { 14 compatible = "fixed-clock"; 15 #clock-cells = <0>; 16 clock-frequency = <600000000>; 17 clock-output-names = "img_pxl_clk"; 18}; 19 20img_subsys: bus@58000000 { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x58000000 0x0 0x58000000 0x1000000>; 25 26 isi: isi@58100000 { 27 reg = <0x58100000 0x80000>; 28 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>; 36 clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>, 37 <&pdma1_lpcg IMX_LPCG_CLK_0>, 38 <&pdma2_lpcg IMX_LPCG_CLK_0>, 39 <&pdma3_lpcg IMX_LPCG_CLK_0>, 40 <&pdma4_lpcg IMX_LPCG_CLK_0>, 41 <&pdma5_lpcg IMX_LPCG_CLK_0>, 42 <&pdma6_lpcg IMX_LPCG_CLK_0>, 43 <&pdma7_lpcg IMX_LPCG_CLK_0>; 44 clock-names = "per0", "per1", "per2", "per3", 45 "per4", "per5", "per6", "per7"; 46 interrupt-parent = <&gic>; 47 power-domains = <&pd IMX_SC_R_ISI_CH0>, 48 <&pd IMX_SC_R_ISI_CH1>, 49 <&pd IMX_SC_R_ISI_CH2>, 50 <&pd IMX_SC_R_ISI_CH3>, 51 <&pd IMX_SC_R_ISI_CH4>, 52 <&pd IMX_SC_R_ISI_CH5>, 53 <&pd IMX_SC_R_ISI_CH6>, 54 <&pd IMX_SC_R_ISI_CH7>; 55 status = "disabled"; 56 }; 57 58 irqsteer_csi0: irqsteer@58220000 { 59 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; 60 reg = <0x58220000 0x1000>; 61 #interrupt-cells = <1>; 62 interrupt-controller; 63 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; 64 clocks = <&img_ipg_clk>; 65 clock-names = "ipg"; 66 interrupt-parent = <&gic>; 67 power-domains = <&pd IMX_SC_R_CSI_0>; 68 fsl,channel = <0>; 69 fsl,num-irqs = <32>; 70 status = "disabled"; 71 }; 72 73 gpio0_mipi_csi0: gpio@58222000 { 74 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 75 reg = <0x58222000 0x1000>; 76 #interrupt-cells = <2>; 77 interrupt-controller; 78 interrupts = <0>; 79 #gpio-cells = <2>; 80 gpio-controller; 81 interrupt-parent = <&irqsteer_csi0>; 82 power-domains = <&pd IMX_SC_R_CSI_0>; 83 }; 84 85 csi0_core_lpcg: clock-controller@58223018 { 86 compatible = "fsl,imx8qxp-lpcg"; 87 reg = <0x58223018 0x4>; 88 clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_PER>; 89 #clock-cells = <1>; 90 clock-indices = <IMX_LPCG_CLK_4>; 91 clock-output-names = "csi0_lpcg_core_clk"; 92 power-domains = <&pd IMX_SC_R_ISI_CH0>; 93 }; 94 95 csi0_esc_lpcg: clock-controller@5822301c { 96 compatible = "fsl,imx8qxp-lpcg"; 97 reg = <0x5822301c 0x4>; 98 clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_MISC>; 99 #clock-cells = <1>; 100 clock-indices = <IMX_LPCG_CLK_4>; 101 clock-output-names = "csi0_lpcg_esc_clk"; 102 power-domains = <&pd IMX_SC_R_ISI_CH0>; 103 }; 104 105 i2c_mipi_csi0: i2c@58226000 { 106 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 107 reg = <0x58226000 0x1000>; 108 interrupts = <8>; 109 clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>, 110 <&img_ipg_clk>; 111 clock-names = "per", "ipg"; 112 assigned-clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>; 113 assigned-clock-rates = <24000000>; 114 interrupt-parent = <&irqsteer_csi0>; 115 power-domains = <&pd IMX_SC_R_CSI_0_I2C_0>; 116 status = "disabled"; 117 }; 118 119 mipi_csi_0: csi@58227000 { 120 compatible = "fsl,imx8qxp-mipi-csi2"; 121 reg = <0x58227000 0x1000>, 122 <0x58221000 0x1000>; 123 clocks = <&csi0_core_lpcg IMX_LPCG_CLK_4>, 124 <&csi0_esc_lpcg IMX_LPCG_CLK_4>, 125 <&csi0_pxl_lpcg IMX_LPCG_CLK_0>; 126 clock-names = "core", "esc", "ui"; 127 assigned-clocks = <&csi0_core_lpcg IMX_LPCG_CLK_4>, 128 <&csi0_esc_lpcg IMX_LPCG_CLK_4>; 129 assigned-clock-rates = <360000000>, <72000000>; 130 power-domains = <&pd IMX_SC_R_ISI_CH0>; 131 resets = <&scu_reset IMX_SC_R_CSI_0>; 132 status = "disabled"; 133 }; 134 135 irqsteer_csi1: irqsteer@58240000 { 136 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; 137 reg = <0x58240000 0x1000>; 138 #interrupt-cells = <1>; 139 interrupt-controller; 140 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&img_ipg_clk>; 142 clock-names = "ipg"; 143 interrupt-parent = <&gic>; 144 power-domains = <&pd IMX_SC_R_CSI_1>; 145 fsl,channel = <0>; 146 fsl,num-irqs = <32>; 147 status = "disabled"; 148 }; 149 150 gpio0_mipi_csi1: gpio@58242000 { 151 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 152 reg = <0x58242000 0x1000>; 153 #interrupt-cells = <2>; 154 interrupt-controller; 155 interrupts = <0>; 156 #gpio-cells = <2>; 157 gpio-controller; 158 interrupt-parent = <&irqsteer_csi1>; 159 power-domains = <&pd IMX_SC_R_CSI_1>; 160 }; 161 162 csi1_core_lpcg: clock-controller@58243018 { 163 compatible = "fsl,imx8qxp-lpcg"; 164 reg = <0x58243018 0x4>; 165 clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_PER>; 166 #clock-cells = <1>; 167 clock-indices = <IMX_LPCG_CLK_4>; 168 clock-output-names = "csi1_lpcg_core_clk"; 169 power-domains = <&pd IMX_SC_R_ISI_CH0>; 170 }; 171 172 csi1_esc_lpcg: clock-controller@5824301c { 173 compatible = "fsl,imx8qxp-lpcg"; 174 reg = <0x5824301c 0x4>; 175 clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_MISC>; 176 #clock-cells = <1>; 177 clock-indices = <IMX_LPCG_CLK_4>; 178 clock-output-names = "csi1_lpcg_esc_clk"; 179 power-domains = <&pd IMX_SC_R_ISI_CH0>; 180 }; 181 182 i2c_mipi_csi1: i2c@58246000 { 183 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 184 reg = <0x58246000 0x1000>; 185 interrupts = <8>; 186 clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>, 187 <&img_ipg_clk>; 188 clock-names = "per", "ipg"; 189 assigned-clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>; 190 assigned-clock-rates = <24000000>; 191 interrupt-parent = <&irqsteer_csi1>; 192 power-domains = <&pd IMX_SC_R_CSI_1_I2C_0>; 193 status = "disabled"; 194 }; 195 196 mipi_csi_1: csi@58247000 { 197 compatible = "fsl,imx8qxp-mipi-csi2"; 198 reg = <0x58247000 0x1000>, 199 <0x58241000 0x1000>; 200 clocks = <&csi1_core_lpcg IMX_LPCG_CLK_4>, 201 <&csi1_esc_lpcg IMX_LPCG_CLK_4>, 202 <&csi1_pxl_lpcg IMX_LPCG_CLK_0>; 203 clock-names = "core", "esc", "ui"; 204 assigned-clocks = <&csi1_core_lpcg IMX_LPCG_CLK_4>, 205 <&csi1_esc_lpcg IMX_LPCG_CLK_4>; 206 assigned-clock-rates = <360000000>, <72000000>; 207 power-domains = <&pd IMX_SC_R_ISI_CH0>; 208 resets = <&scu_reset IMX_SC_R_CSI_1>; 209 status = "disabled"; 210 }; 211 212 irqsteer_parallel: irqsteer@58260000 { 213 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; 214 reg = <0x58260000 0x1000>; 215 #interrupt-cells = <1>; 216 interrupt-controller; 217 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&clk_dummy>; 219 clock-names = "ipg"; 220 interrupt-parent = <&gic>; 221 power-domains = <&pd IMX_SC_R_PI_0>; 222 fsl,channel = <0>; 223 fsl,num-irqs = <32>; 224 status = "disabled"; 225 }; 226 227 pi0_ipg_lpcg: clock-controller@58263004 { 228 compatible = "fsl,imx8qxp-lpcg"; 229 reg = <0x58263004 0x4>; 230 clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; 231 #clock-cells = <1>; 232 clock-indices = <IMX_LPCG_CLK_4>; 233 clock-output-names = "pi0_lpcg_ipg_clk"; 234 power-domains = <&pd IMX_SC_R_ISI_CH0>; 235 }; 236 237 pi0_pxl_lpcg: clock-controller@58263018 { 238 compatible = "fsl,imx8qxp-lpcg"; 239 reg = <0x58263018 0x4>; 240 clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; 241 #clock-cells = <1>; 242 clock-indices = <IMX_LPCG_CLK_0>; 243 clock-output-names = "pi0_lpcg_pxl_clk"; 244 power-domains = <&pd IMX_SC_R_ISI_CH0>; 245 }; 246 247 pi0_misc_lpcg: clock-controller@5826301c { 248 compatible = "fsl,imx8qxp-lpcg"; 249 reg = <0x5826301c 0x4>; 250 clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_MISC0>; 251 #clock-cells = <1>; 252 clock-indices = <IMX_LPCG_CLK_0>; 253 clock-output-names = "pi0_lpcg_misc_clk"; 254 power-domains = <&pd IMX_SC_R_ISI_CH0>; 255 }; 256 257 i2c0_parallel: i2c@58266000 { 258 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 259 reg = <0x58266000 0x1000>; 260 interrupts = <8>; 261 clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>, 262 <&img_ipg_clk>; 263 clock-names = "per", "ipg"; 264 assigned-clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>; 265 assigned-clock-rates = <24000000>; 266 interrupt-parent = <&irqsteer_parallel>; 267 power-domains = <&pd IMX_SC_R_PI_0_I2C_0>; 268 status = "disabled"; 269 }; 270 271 jpegdec: jpegdec@58400000 { 272 reg = <0x58400000 0x00050000>; 273 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>, 275 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; 276 assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>, 277 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; 278 assigned-clock-rates = <200000000>, <200000000>; 279 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>, 280 <&pd IMX_SC_R_MJPEG_DEC_S0>; 281 }; 282 283 jpegenc: jpegenc@58450000 { 284 reg = <0x58450000 0x00050000>; 285 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>, 287 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; 288 assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>, 289 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; 290 assigned-clock-rates = <200000000>, <200000000>; 291 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>, 292 <&pd IMX_SC_R_MJPEG_ENC_S0>; 293 }; 294 295 pdma0_lpcg: clock-controller@58500000 { 296 compatible = "fsl,imx8qxp-lpcg"; 297 reg = <0x58500000 0x10000>; 298 clocks = <&img_pxl_clk>; 299 #clock-cells = <1>; 300 clock-indices = <IMX_LPCG_CLK_0>; 301 clock-output-names = "pdma0_lpcg_clk"; 302 power-domains = <&pd IMX_SC_R_ISI_CH0>; 303 }; 304 305 pdma1_lpcg: clock-controller@58510000 { 306 compatible = "fsl,imx8qxp-lpcg"; 307 reg = <0x58510000 0x10000>; 308 clocks = <&img_pxl_clk>; 309 #clock-cells = <1>; 310 clock-indices = <IMX_LPCG_CLK_0>; 311 clock-output-names = "pdma1_lpcg_clk"; 312 power-domains = <&pd IMX_SC_R_ISI_CH1>; 313 }; 314 315 pdma2_lpcg: clock-controller@58520000 { 316 compatible = "fsl,imx8qxp-lpcg"; 317 reg = <0x58520000 0x10000>; 318 clocks = <&img_pxl_clk>; 319 #clock-cells = <1>; 320 clock-indices = <IMX_LPCG_CLK_0>; 321 clock-output-names = "pdma2_lpcg_clk"; 322 power-domains = <&pd IMX_SC_R_ISI_CH2>; 323 }; 324 325 pdma3_lpcg: clock-controller@58530000 { 326 compatible = "fsl,imx8qxp-lpcg"; 327 reg = <0x58530000 0x10000>; 328 clocks = <&img_pxl_clk>; 329 #clock-cells = <1>; 330 clock-indices = <IMX_LPCG_CLK_0>; 331 clock-output-names = "pdma3_lpcg_clk"; 332 power-domains = <&pd IMX_SC_R_ISI_CH3>; 333 }; 334 335 pdma4_lpcg: clock-controller@58540000 { 336 compatible = "fsl,imx8qxp-lpcg"; 337 reg = <0x58540000 0x10000>; 338 clocks = <&img_pxl_clk>; 339 #clock-cells = <1>; 340 clock-indices = <IMX_LPCG_CLK_0>; 341 clock-output-names = "pdma4_lpcg_clk"; 342 power-domains = <&pd IMX_SC_R_ISI_CH4>; 343 }; 344 345 pdma5_lpcg: clock-controller@58550000 { 346 compatible = "fsl,imx8qxp-lpcg"; 347 reg = <0x58550000 0x10000>; 348 clocks = <&img_pxl_clk>; 349 #clock-cells = <1>; 350 clock-indices = <IMX_LPCG_CLK_0>; 351 clock-output-names = "pdma5_lpcg_clk"; 352 power-domains = <&pd IMX_SC_R_ISI_CH5>; 353 }; 354 355 pdma6_lpcg: clock-controller@58560000 { 356 compatible = "fsl,imx8qxp-lpcg"; 357 reg = <0x58560000 0x10000>; 358 clocks = <&img_pxl_clk>; 359 #clock-cells = <1>; 360 clock-indices = <IMX_LPCG_CLK_0>; 361 clock-output-names = "pdma6_lpcg_clk"; 362 power-domains = <&pd IMX_SC_R_ISI_CH6>; 363 }; 364 365 pdma7_lpcg: clock-controller@58570000 { 366 compatible = "fsl,imx8qxp-lpcg"; 367 reg = <0x58570000 0x10000>; 368 clocks = <&img_pxl_clk>; 369 #clock-cells = <1>; 370 clock-indices = <IMX_LPCG_CLK_0>; 371 clock-output-names = "pdma7_lpcg_clk"; 372 power-domains = <&pd IMX_SC_R_ISI_CH7>; 373 }; 374 375 csi0_pxl_lpcg: clock-controller@58580000 { 376 compatible = "fsl,imx8qxp-lpcg"; 377 reg = <0x58580000 0x10000>; 378 clocks = <&img_pxl_clk>; 379 #clock-cells = <1>; 380 clock-indices = <IMX_LPCG_CLK_0>; 381 clock-output-names = "csi0_lpcg_pxl_clk"; 382 power-domains = <&pd IMX_SC_R_CSI_0>; 383 }; 384 385 csi1_pxl_lpcg: clock-controller@58590000 { 386 compatible = "fsl,imx8qxp-lpcg"; 387 reg = <0x58590000 0x10000>; 388 clocks = <&img_pxl_clk>; 389 #clock-cells = <1>; 390 clock-indices = <IMX_LPCG_CLK_0>; 391 clock-output-names = "csi1_lpcg_pxl_clk"; 392 power-domains = <&pd IMX_SC_R_CSI_1>; 393 }; 394 395 hdmi_rx_pxl_link_lpcg: clock-controller@585a0000 { 396 compatible = "fsl,imx8qxp-lpcg"; 397 reg = <0x585a0000 0x10000>; 398 clocks = <&img_pxl_clk>; 399 #clock-cells = <1>; 400 clock-indices = <IMX_LPCG_CLK_0>; 401 clock-output-names = "hdmi_rx_lpcg_pxl_link_clk"; 402 power-domains = <&pd IMX_SC_R_HDMI_RX>; 403 }; 404 405 img_jpeg_dec_lpcg: clock-controller@585d0000 { 406 compatible = "fsl,imx8qxp-lpcg"; 407 reg = <0x585d0000 0x10000>; 408 #clock-cells = <1>; 409 clocks = <&img_ipg_clk>, <&img_ipg_clk>; 410 clock-indices = <IMX_LPCG_CLK_0>, 411 <IMX_LPCG_CLK_4>; 412 clock-output-names = "img_jpeg_dec_lpcg_clk", 413 "img_jpeg_dec_lpcg_ipg_clk"; 414 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>; 415 }; 416 417 img_jpeg_enc_lpcg: clock-controller@585f0000 { 418 compatible = "fsl,imx8qxp-lpcg"; 419 reg = <0x585f0000 0x10000>; 420 #clock-cells = <1>; 421 clocks = <&img_ipg_clk>, <&img_ipg_clk>; 422 clock-indices = <IMX_LPCG_CLK_0>, 423 <IMX_LPCG_CLK_4>; 424 clock-output-names = "img_jpeg_enc_lpcg_clk", 425 "img_jpeg_enc_lpcg_ipg_clk"; 426 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>; 427 }; 428}; 429