| /linux/drivers/memory/ |
| H A D | jedec_ddr_data.c | 54 /* Speed bin 533(266 MHz) */
96 /* Speed bin 1066(533 MHz) */
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| /linux/drivers/crypto/intel/qat/qat_c62x/ |
| H A D | adf_c62x_hw_data.h | 26 #define ADF_C62X_MIN_AE_FREQ (533 * HZ_PER_MHZ)
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| /linux/drivers/crypto/intel/qat/qat_c3xxx/ |
| H A D | adf_c3xxx_hw_data.h | 26 #define ADF_C3XXX_MIN_AE_FREQ (533 * HZ_PER_MHZ)
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| /linux/drivers/interconnect/qcom/ |
| H A D | sdx65.h | 50 #define SDX65_SLAVE_TCSR 533
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| H A D | qdu1000.h | 63 #define QDU1000_SLAVE_QUP_1 533
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| H A D | sm8450.h | 96 #define SM8450_SLAVE_LPASS_MPU_CFG 533
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| H A D | sc8280xp.h | 107 #define SC8280XP_SLAVE_EMAC1_CFG 533
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| /linux/arch/arm/boot/dts/intel/ixp/ |
| H A D | intel-ixp42x-ixdp425.dts | 8 * This machine is based on a 533 MHz IXP425.
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| /linux/drivers/video/fbdev/mb862xx/ |
| H A D | mb862xx_reg.h | 187 #define GC_DISP_REFCLK_533 533
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | qcom,pcie-sc8280xp.yaml | 156 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
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| /linux/fs/afs/ |
| H A D | afs_vl.h | 24 VLGETADDRSU = 533, /* AFS Get addrs for fileserver */
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| /linux/arch/arm/boot/dts/nvidia/ |
| H A D | tegra30-lg-p895.dts | 117 /* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */
194 /* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */
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| /linux/sound/isa/gus/ |
| H A D | gus_tables.h | 48 533 /* 30 */,521 /* 31 */,509 /* 32 */,498 /* 33 */,487 /* 34 */,
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| /linux/drivers/net/wireless/ath/ |
| H A D | regd.h | 66 CTRY_ARUBA = 533,
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| /linux/drivers/clk/mvebu/ |
| H A D | dove.c | 34 * 13 = 533 MHz
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| /linux/arch/x86/entry/syscalls/ |
| H A D | syscall_64.tbl | 425 533 x32 move_pages sys_move_pages
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| /linux/tools/perf/arch/x86/entry/syscalls/ |
| H A D | syscall_64.tbl | 424 533 x32 move_pages sys_move_pages
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| /linux/drivers/clk/renesas/ |
| H A D | rzg2l-cpg.c | 207 * As per the HW manual, we should not directly switch from 533 MHz to in rzg2l_cpg_sd_clk_mux_notifier()
208 * 400 MHz and vice versa. To change the setting from 2’b01 (533 MHz) in rzg2l_cpg_sd_clk_mux_notifier()
210 * and then switch to the target setting (2’b01 (533 MHz) or 2’b10 in rzg2l_cpg_sd_clk_mux_notifier()
214 * The clock mux has 3 input clocks(533 MHz, 400 MHz, and 266 MHz), and in rzg2l_cpg_sd_clk_mux_notifier()
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| /linux/include/dt-bindings/clock/ |
| H A D | rockchip,rk3576-cru.h | 551 #define HCLK_CRYPTO_NS 533
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| H A D | rockchip,rk3588-cru.h | 548 #define CLK_HDMITX1_REF 533
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| /linux/drivers/bus/ |
| H A D | intel-ixp4xx-eb.c | 381 dev_info(dev, "IXP43x at 533 MHz\n"); in ixp4xx_exp_probe()
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| /linux/include/dt-bindings/firmware/imx/ |
| H A D | rsrc.h | 550 #define IMX_SC_R_MJPEG_0_ENC_MP 533
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| /linux/include/dt-bindings/gce/ |
| H A D | mt8195-gce.h | 451 #define CMDQ_EVENT_VDO0_DP_INTF0_SOF 533
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| /linux/drivers/clk/starfive/ |
| H A D | clk-starfive-jh7110-pll.c | 221 .fbdiv = 533,
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| /linux/include/dt-bindings/mailbox/ |
| H A D | mediatek,mt8188-gce.h | 487 #define CMDQ_EVENT_VDO0_DP_INTF0_SOF 533
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