| /linux/drivers/clk/qcom/ |
| H A D | ipq-cmn-pll.c | 13 * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock
14 * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch),
15 * and one clock with 353 MHZ to PPE. The other fixed rate output clocks
16 * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS
17 * with 31.25 MHZ.
19 * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ,
20 * and an output clock to NSS (network subsystem) at 300 MHZ. The other output
29 * | +-------------> eth0-50mhz
31 * -------->+ +-------------> eth1-50mhz
33 * | +-------------> eth2-50mhz
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| /linux/arch/m68k/include/uapi/asm/ |
| H A D | bootinfo-hp300.h | 25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
26 #define HP_330 1 /* 16MHz 68020+68851 MMU */
27 #define HP_340 2 /* 16MHz 68030 */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
30 #define HP_360 5 /* 25MHz 68030 */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
32 #define HP_375 7 /* 50MHz 68030+32K external cache */
33 #define HP_380 8 /* 25MHz 68040 */
34 #define HP_385 9 /* 33MHz 68040 */
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| /linux/Documentation/scsi/ |
| H A D | aic7xxx.rst | 26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
34 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
35 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
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| /linux/net/wireless/tests/ |
| H A D | chan.c | 44 .desc = "identical 20 MHz",
53 .desc = "identical 40 MHz",
62 .desc = "identical 80 MHz",
71 .desc = "identical 160 MHz",
80 .desc = "identical 320 MHz",
89 .desc = "20 MHz in 320 MHz\n",
103 .desc = "different 20 MHz",
116 .desc = "different primary 320 MHz",
125 .center_freq1 = 6475 - 50,
130 .desc = "matching primary 160 MHz",
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| /linux/drivers/phy/intel/ |
| H A D | phy-intel-keembay-emmc.c | 59 unsigned int mhz; in keembay_emmc_phy_power() local
84 mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000); in keembay_emmc_phy_power()
85 if (mhz <= 200 && mhz >= 170) in keembay_emmc_phy_power()
87 else if (mhz <= 170 && mhz >= 140) in keembay_emmc_phy_power()
89 else if (mhz <= 140 && mhz >= 110) in keembay_emmc_phy_power()
91 else if (mhz <= 110 && mhz >= 80) in keembay_emmc_phy_power()
93 else if (mhz <= 80 && mhz >= 50) in keembay_emmc_phy_power()
99 if (mhz > 175) in keembay_emmc_phy_power()
100 dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz); in keembay_emmc_phy_power()
125 0, 50); in keembay_emmc_phy_power()
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| /linux/arch/arm/mach-omap2/ |
| H A D | opp2xxx.h | 123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
136 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
141 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
144 /* 2420-PRCM II 600MHz core */
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| /linux/drivers/clk/uniphier/ |
| H A D | clk-uniphier-sys.c | 28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
33 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
36 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \
37 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0)
87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
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| /linux/Documentation/fb/ |
| H A D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
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| /linux/drivers/ata/ |
| H A D | pata_ftide010.c | 79 /* 0 = 50 MHz, 1 = 66 MHz */
94 * reference clock which is 30 nanoseconds per unit at 66MHz and 20
95 * nanoseconds per unit at 50 MHz. The PIO timings assume 33MHz speed for
103 * word DMA, Mode 0, 1, and 2 at 50 MHz. Range 0..15.
105 * multi word DMA, Mode 0, 1 and 2 at 50 MHz. Range 0..15.
107 * word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
109 * multi word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
111 * DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz. Range 0..7.
113 * multi word DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz, Range 0..7.
115 * word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
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| H A D | pata_hpt37x.c | 595 * @freq: Reported frequency in MHz
597 * Turn the timing data into a clock slot (0 for 33, 1 for 40, 2 for 50
598 * and 3 for 66Mhz)
604 return 0; /* 33Mhz slot */ in hpt37x_clock_slot()
606 return 1; /* 40Mhz slot */ in hpt37x_clock_slot()
608 return 2; /* 50Mhz slot */ in hpt37x_clock_slot()
609 return 3; /* 60Mhz slot */ in hpt37x_clock_slot()
627 udelay(50); in hpt37x_calibrate_dpll()
688 freq = (fcnt * base) / 192; /* in MHz */ in hpt37x_pci_clock()
696 return 50; in hpt37x_pci_clock()
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| /linux/drivers/net/wireless/intel/iwlwifi/mvm/ |
| H A D | rfi.c | 11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
16 {cpu_to_le16(160), {50, 58, 60, 62, 64, 52, 54, 56},
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
42 /* frequency 4267MHz */
47 /* frequency 4400MHz */
52 /* frequency 5200MHz */
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | nxp,tja11xx.yaml | 54 typically derived from an external 25MHz crystal. Alternatively,
55 a 50MHz clock signal generated by an external oscillator can be
56 connected to pin REF_CLK. A third option is to connect a 25MHz
79 description: Enable 50MHz RMII reference clock output on REF_CLK pin.
|
| /linux/arch/arm/mach-pxa/ |
| H A D | sleep.S | 62 @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
67 @ with core operating above 91 MHz
68 @ (see Errata 50, ...processor does not exit from sleep...)
104 @ about suspending with PXBus operating above 133MHz
124 orrne r7, r7, #1 @@ 99.53MHz
151 @ need 6 13-MHz cycles before changing PWRMODE
152 @ just set frequency to 91-MHz... 6*91/13 = 42
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | starfive,jh7100-clkgen.yaml | 22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
|
| /linux/Documentation/admin-guide/media/ |
| H A D | vivid.rst | 344 supports frames per second settings of 10, 15, 25, 30, 50 and 60 fps. Which ones
367 visible. For 50 Hz standards the top field is the oldest and the bottom field
372 contain the top field for 50 Hz standards and the bottom field for 60 Hz
387 The TV 'tuner' supports a frequency range of 44-958 MHz. Channels are available
388 every 6 MHz, starting from 49.25 MHz. For each channel the generated image
389 will be in color for the +/- 0.25 MHz around it, and in grayscale for
390 +/- 1 MHz around the channel. Beyond that it is just noise. The VIDIOC_G_TUNER
391 ioctl will return 100% signal strength for +/- 0.25 MHz and 50% for +/- 1 MHz.
395 The audio subchannels that are returned are MONO for the +/- 1 MHz range around
396 a valid channel frequency. When the frequency is within +/- 0.25 MHz of the
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| /linux/drivers/gpu/drm/tests/ |
| H A D | drm_kunit_edid.h | 41 * DTD 1: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz (1600 mm x 900 mm)
46 * Monitor ranges (GTF): 50-70 Hz V, 30-70 kHz H, max dotclock 150 MHz
73 * This edid is intentionally broken with the 100MHz limit. It's meant
117 * DMT 0x04: 640x480 59.940476 Hz 4:3 31.469 kHz 25.175000 MHz
120 * DTD 1: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz (1600 mm x 900 mm)
125 * Monitor ranges (GTF): 50-70 Hz V, 30-70 kHz H, max dotclock 150 MHz
139 * VIC 16: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz
148 * Maximum TMDS clock: 100 MHz
230 * DMT 0x04: 640x480 59.940476 Hz 4:3 31.469 kHz 25.175000 MHz
233 * DTD 1: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz (1600 mm x 900 mm)
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| H A D | drm_modes_test.c | 62 * pixel clock of 13.5 MHz, a pixel takes around 74ns, so we in drm_test_modes_analog_tv_ntsc_480i()
112 KUNIT_EXPECT_EQ(test, drm_mode_vrefresh(mode), 50); in drm_test_modes_analog_tv_pal_576i()
120 * clock of 13.5 MHz, a pixel takes around 74ns, so we need to in drm_test_modes_analog_tv_pal_576i()
170 KUNIT_EXPECT_EQ(test, drm_mode_vrefresh(mode), 50); in drm_test_modes_analog_tv_mono_576i()
178 * clock of 13.5 MHz, a pixel takes around 74ns, so we need to in drm_test_modes_analog_tv_mono_576i()
|
| /linux/drivers/cpufreq/ |
| H A D | pxa2xx-cpufreq.c | 42 MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
62 { 99500, -1, -1}, /* 99, 99, 50, 50 */
74 { 99500, -1, -1}, /* 99, 99, 50, 50 */
75 {199100, -1, -1}, /* 99, 199, 50, 99 */
76 {298500, -1, -1}, /* 99, 287, 50, 99 */
198 pr_debug("Changing CPU frequency from %d Mhz to %d Mhz\n", in pxa_set_target()
|
| /linux/drivers/net/dsa/sja1105/ |
| H A D | sja1105_clocking.c | 130 idiv.clksrc = 0x0A; /* 25MHz */ in sja1105_cgu_idiv_config()
362 /* RGMII: 125MHz for 1000, 25MHz for 100, 2.5MHz for 10 */ in sja1105_cgu_rgmii_tx_clk_config()
485 * 0 = 2.5MHz in sja1110_cfg_pad_mii_id_packing()
486 * 1 = 25MHz in sja1110_cfg_pad_mii_id_packing()
487 * 2 = 50MHz in sja1110_cfg_pad_mii_id_packing()
488 * 3 = 125MHz in sja1110_cfg_pad_mii_id_packing()
601 /* 1000Mbps, IDIV disabled (125 MHz) */ in sja1105_rgmii_clocking_setup()
604 /* 100Mbps, IDIV enabled, divide by 1 (25 MHz) */ in sja1105_rgmii_clocking_setup()
607 /* 10Mbps, IDIV enabled, divide by 10 (2.5 MHz) */ in sja1105_rgmii_clocking_setup()
698 /* PLL1 must be enabled and output 50 Mhz. in sja1105_cgu_rmii_pll_config()
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| /linux/drivers/scsi/ |
| H A D | dc395x.h | 31 #define DC395x_SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */
343 /* 000 100ns, 10.0 MHz */
344 /* 001 150ns, 6.6 MHz */
345 /* 010 200ns, 5.0 MHz */
346 /* 011 250ns, 4.0 MHz */
347 /* 100 300ns, 3.3 MHz */
348 /* 101 350ns, 2.8 MHz */
349 /* 110 400ns, 2.5 MHz */
350 /* 111 450ns, 2.2 MHz */
355 /* 000 50ns, 20.0 MHz */
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| /linux/drivers/media/pci/mantis/ |
| H A D | mantis_vp3030.c | 31 .name = "ENV57H12D5 (ET-50DT)",
33 .frequency_min = 47 * MHz,
34 .frequency_max = 862 * MHz,
36 .ref_multiplier = 6, /* 1/6 MHz */
37 .ref_divider = 100000, /* 1/6 MHz */
|
| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | am5729-beagleboneai.dts | 422 st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */
444 * 50 mA typical 80 mA max touchscreen drivers
554 /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */
555 /* HS: High speed up to 50 MHz (3.3 V signaling). */
556 /* SDR12: SDR up to 25 MHz (1.8 V signaling). */
557 /* SDR25: SDR up to 50 MHz (1.8 V signaling). */
558 /* SDR50: SDR up to 100 MHz (1.8 V signaling). */
559 /* SDR104: SDR up to 208 MHz (1.8 V signaling) */
560 /* DDR50: DDR up to 50 MHz (1.8 V signaling). */
|
| /linux/drivers/clk/ |
| H A D | kunit_clk_parent_data_test.dtso | 8 fixed_50: kunit-clock-50MHz {
15 fixed_parent: kunit-clock-1MHz {
|
| /linux/drivers/clk/versatile/ |
| H A D | clk-icst.c | 108 * 33 or 25 MHz respectively. in vco_get()
271 /* Divides between 3 and 50 MHz in steps of 0.25 MHz */ in icst_determine_rate()
277 /* Slam to closest 0.25 MHz */ in icst_determine_rate()
286 * If we're below or less than halfway from 25 to 33 MHz in icst_determine_rate()
287 * select 25 MHz in icst_determine_rate()
457 /* Minimum 12 MHz, VDW = 4 */
460 * Maximum 160 MHz, VDW = 152 for all core modules, but
462 * go to 200 MHz (max VDW = 192).
475 /* Minimum 3 MHz, VDW = 4 */
477 /* Maximum 50 MHz, VDW = 192 */
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| /linux/Documentation/devicetree/bindings/media/i2c/ |
| H A D | sony,imx335.yaml | 28 description: Clock frequency from 6 to 27 MHz, 37.125MHz, 74.25MHz
89 reset-gpios = <&gpio 50 GPIO_ACTIVE_LOW>;
|