/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | armada3700-periph-clock.txt | 36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet 38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet 39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1 40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0 41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1 42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
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H A D | starfive,jh7100-clkgen.yaml | 22 - description: Main clock source (25 MHz) 23 - description: Application-specific clock source (12-27 MHz) 24 - description: RMII reference clock (50 MHz) 25 - description: RGMII RX clock (125 MHz)
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H A D | st,stm32mp25-rcc.yaml | 36 - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz) 37 - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz) 38 - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz) 93 - description: CK_SCMI_FLEXGEN_50 flexgen clock 50
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/freebsd/sys/contrib/device-tree/Bindings/input/touchscreen/ |
H A D | stmpe.txt | 15 1 -> 50 us 21 7 -> 50 ms 29 6 -> 50 ms 35 1 -> 50 mA (typical 80 mA max) 53 0 -> 1.625 MHz 54 1 -> 3.25 MHz 55 2 || 3 -> 6.5 MHz 78 /* 3.25 MHz ADC clock speed */ 99 * 50 mA typical 80 mA max touchscreen drivers
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/freebsd/sys/contrib/dev/iwlwifi/mvm/ |
H A D | rfi.c | 11 * DDR needs frequency in units of 16.666MHz, so provide FW with the 15 /* frequency 2667MHz */ 16 {cpu_to_le16(160), {50, 58, 60, 62, 64, 52, 54, 56}, 20 /* frequency 2933MHz */ 27 /* frequency 3200MHz */ 32 /* frequency 3733MHz */ 37 /* frequency 4000MHz */ 42 /* frequency 4267MHz */ 47 /* frequency 4400MHz */ 52 /* frequency 5200MHz */ [all...] |
/freebsd/sys/dev/sfxge/common/ |
H A D | ef10_tlv_layout.h | 459 uint16_t clk_sys; /* MHz */ 460 uint16_t clk_dpcpu; /* MHz */ 461 uint16_t clk_icore; /* MHz */ 462 uint16_t clk_pcs; /* MHz */ 470 uint16_t clk_sys; /* MHz */ 471 uint16_t clk_mc; /* MHz */ 472 uint16_t clk_rmon; /* MHz */ 473 uint16_t clk_vswitch; /* MHz */ 474 uint16_t clk_dpcpu; /* MHz */ 475 uint16_t clk_pcs; /* MHz */ [all …]
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/freebsd/sys/contrib/device-tree/Bindings/net/ |
H A D | micrel.txt | 23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select 24 bit selects 25 MHz mode 26 Setting the RMII Reference Clock Select bit enables 25 MHz rather 27 than 50 MHz clock mode.
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H A D | ti,dp83822.yaml | 87 - RMII master, where the PHY outputs a 50MHz reference clock which can 89 - RMII slave, where the PHY expects a 50MHz reference clock input
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H A D | nxp,tja11xx.yaml | 54 typically derived from an external 25MHz crystal. Alternatively, 55 a 50MHz clock signal generated by an external oscillator can be 56 connected to pin REF_CLK. A third option is to connect a 25MHz
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H A D | stm32-dwmac.yaml | 94 set this property in RMII mode when you have PHY without crystal 50MHz and want to 106 set this property in RMII mode when you have PHY without crystal 50MHz and want to
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H A D | rockchip-dwmac.txt | 32 - clock_in_out: For RGMII, it must be "input", means main clock(125MHz) 34 PHY provides the reference clock(50MHz), "output" means GMAC provides the
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H A D | rockchip-dwmac.yaml | 79 For RGMII, it must be "input", means main clock(125MHz) 81 For RMII, "input" means PHY provides the reference clock(50MHz),
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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
H A D | ar9300_radio.c | 63 * Take the MHz channel value and set the Channel value 71 * (freq_ref = 40MHz) 75 * (freq_ref = 40MHz/(24>>amode_ref_sel)) 77 * For 5GHz channels which are 5MHz spaced, 79 * (freq_ref = 40MHz) 154 * freq_ref = (50 / (refdiva >> a_mode_ref_sel)); in ar9300_set_channel() 169 * freq_ref = (50 / (refdiva >> a_mode_ref_sel)); in ar9300_set_channel() 192 * freq_ref = (50 / (refdiva >> amoderefsel)); in ar9300_set_channel()
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
H A D | am5729-beagleboneai.dts | 422 st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ 444 * 50 mA typical 80 mA max touchscreen drivers 555 /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */ 556 /* HS: High speed up to 50 MHz (3.3 V signaling). */ 557 /* SDR12: SDR up to 25 MHz (1.8 V signaling). */ 558 /* SDR25: SDR up to 50 MHz (1.8 V signaling). */ 559 /* SDR50: SDR up to 100 MHz (1.8 V signaling). */ 560 /* SDR104: SDR up to 208 MHz (1.8 V signaling) */ 561 /* DDR50: DDR up to 50 MHz (1.8 V signaling). */
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/freebsd/sys/arm/freescale/imx/ |
H A D | imx6_anatop.c | 119 * 396MHz, it also says that the ARM and SOC voltages can't differ by 124 uint32_t mhz; member 136 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked 170 * can't be more than 50mV above or 200mV below them. We keep them the in vdd_set() 266 d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz); in cpufreq_nearest_oppt() 281 if (op->mhz > sc->cpu_curmhz) { in cpufreq_set_clock() 289 * - Set the PLL into bypass mode; cpu should now be running at 24mhz. in cpufreq_set_clock() 291 * - Wait for the LOCK bit to come on; it takes ~50 loop iterations. in cpufreq_set_clock() 294 cpufreq_mhz_to_div(sc, op->mhz, &corediv, &plldiv); in cpufreq_set_clock() 316 if (op->mhz < sc->cpu_curmhz) in cpufreq_set_clock() [all …]
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/freebsd/contrib/wpa/wpa_supplicant/ |
H A D | op_classes.c | 59 * In 80 MHz, the bandwidth "spans" 12 channels (e.g., 36-48), in get_center_80mhz() 129 * In 160 MHz, the bandwidth "spans" 28 channels (e.g., 36-64), in get_center_160mhz() 149 const u8 center_channels_5ghz[] = { 50, 114, 163 }; in verify_160mhz() 199 * In 320 MHz, the bandwidth "spans" 60 channels (e.g., 65-125), in get_center_320mhz() 275 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel() 276 * result and use only the 80 MHz specific version. in verify_channel() 282 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel() 283 * result and use only the 160 MHz specific version. in verify_channel() 289 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel() 290 * result and use only the 80 MHz specific version. in verify_channel() [all …]
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/freebsd/sys/contrib/device-tree/Bindings/media/i2c/ |
H A D | sony,imx335.yaml | 32 description: Clock frequency from 6 to 27 MHz, 37.125MHz, 74.25MHz 97 reset-gpios = <&gpio 50 GPIO_ACTIVE_LOW>;
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
H A D | imx6sx-softing-vining-2000.dts | 417 pinctrl_usdhc2_50mhz: usdhc2grp-50mhz { 430 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { 441 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { 452 pinctrl_usdhc4_50mhz: usdhc4grp-50mhz { 468 pinctrl_usdhc4_100mhz: usdhc4-100mhz { 483 pinctrl_usdhc4_200mhz: usdhc4-200mhz {
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/freebsd/sys/dts/arm/ |
H A D | zybo.dts | 47 clock-frequency = <50000000>; // 50Mhz PS_CLK 51 clock-frequency = <325000000>; // 325Mhz
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H A D | zynq-7000.dtsi | 146 interrupts = <0 50 4>; 204 ref-clock = <200000000>; // 200 Mhz 205 spi-clock = <50000000>; // 50 Mhz
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/freebsd/sys/contrib/device-tree/src/powerpc/ |
H A D | ac14xx.dts | 26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */ 27 bus-frequency = <160000000>; /* 160 MHz csb bus */ 28 clock-frequency = <400000000>; /* 400 MHz ppc core */ 145 bus-frequency = <80000000>; /* 80 MHz ips bus */ 189 at24@50 { 258 1E 4C 50 00 00 00 01 01 01 01 01 01 01 01 01 01
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/freebsd/sys/contrib/dev/athk/ |
H A D | dfs_pattern_detector.c | 37 #define MIN_PPB_THRESH 50 43 #define WIDTH_LOWER(X) ((X*(100-WIDTH_TOLERANCE)+50)/100) 44 #define WIDTH_UPPER(X) ((X*(100+WIDTH_TOLERANCE)+50)/100) 93 FCC_PATTERN(5, 50, 100, 1000, 2000, 1, 1, true), 113 JP_PATTERN(2, 0, 1, 1388, 1388, 1, 18, 50, false), 114 JP_PATTERN(3, 0, 4, 4000, 4000, 1, 18, 50, false), 115 JP_PATTERN(4, 0, 5, 150, 230, 1, 23, 50, false), 116 JP_PATTERN(5, 6, 10, 200, 500, 1, 16, 50, false), 117 JP_PATTERN(6, 11, 20, 200, 500, 1, 12, 50, false), 118 JP_PATTERN(7, 50, 100, 1000, 2000, 1, 3, 50, true), [all …]
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/freebsd/sys/contrib/device-tree/Bindings/mmc/ |
H A D | sdhci-st.txt | 41 - max-frequency: Can be 200MHz, 100MHz or 50MHz (default) and used for
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/freebsd/sys/contrib/dev/iwlwifi/cfg/ |
H A D | 22000.c | 205 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz"; 206 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz"; 208 const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz"; 211 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)"; 213 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)"; 215 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)"; 217 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)"; 245 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 283 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 309 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", [all...] |
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
H A D | intel,pinctrl-keembay.yaml | 78 0 - Fast(~100MHz) 79 1 - Slow(~50MHz)
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