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/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_regs.h35 #define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4)
38 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\ argument
39 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
40 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\ argument
41 FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
44 #define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4)
47 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\ argument
48 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
49 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\ argument
50 FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
[all …]
/linux/include/soc/mscc/
H A Docelot_dev.h14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
17 #define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0)) argument
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
27 #define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15)) argument
29 #define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15) argument
30 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8)) argument
32 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8) argument
33 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1)) argument
35 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x) (((x) & GENMASK(7, 1)) >> 1) argument
38 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x) (((x) << 4) & GENMASK(11, 4)) argument
[all …]
H A Docelot_hsio.h90 #define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23)) argument
92 #define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23) argument
93 #define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18)) argument
95 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18) argument
96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16)) argument
98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16) argument
103 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6)) argument
105 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV_X(x) (((x) & GENMASK(11, 6)) >> 6) argument
106 #define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0)) argument
114 #define HSIO_PLL5G_CFG1_RC_CTRL_DATA(x) (((x) << 6) & GENMASK(13, 6)) argument
[all …]
H A Docelot_qsys.h17 #define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE BIT(4)
25 #define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8)) argument
27 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8) argument
28 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0)) argument
33 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8)) argument
35 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8) argument
36 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0)) argument
41 #define QSYS_QMAP_SE_BASE(x) (((x) << 5) & GENMASK(12, 5)) argument
43 #define QSYS_QMAP_SE_BASE_X(x) (((x) & GENMASK(12, 5)) >> 5) argument
44 #define QSYS_QMAP_SE_IDX_SEL(x) (((x) << 2) & GENMASK(4, 2)) argument
[all …]
/linux/arch/mips/include/asm/sibyte/
H A Dsb1250_scd.h29 * System Revision Register (Table 4-1)
36 #define V_SYS_REVISION(x) _SB_MAKEVALUE(x, S_SYS_REVISION) argument
37 #define G_SYS_REVISION(x) _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION) argument
84 #define M_SYS_L2C_SIZE _SB_MAKEMASK(4, S_SYS_L2C_SIZE)
85 #define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x, S_SYS_L2C_SIZE) argument
86 #define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE) argument
100 #define M_SYS_NUM_CPUS _SB_MAKEMASK(4, S_SYS_NUM_CPUS)
101 #define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x, S_SYS_NUM_CPUS) argument
102 #define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS) argument
108 #define V_SYS_PART(x) _SB_MAKEVALUE(x, S_SYS_PART) argument
[all …]
H A Dsb1250_mc.h34 #define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL) argument
35 #define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL) argument
38 #define M_MC_BANK0_MAP _SB_MAKEMASK(4, S_MC_BANK0_MAP)
39 #define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK0_MAP) argument
40 #define G_MC_BANK0_MAP(x) _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP) argument
46 #define M_MC_BANK1_MAP _SB_MAKEMASK(4, S_MC_BANK1_MAP)
47 #define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK1_MAP) argument
48 #define G_MC_BANK1_MAP(x) _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP) argument
54 #define M_MC_BANK2_MAP _SB_MAKEMASK(4, S_MC_BANK2_MAP)
55 #define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK2_MAP) argument
[all …]
H A Dbcm1480_mc.h31 #define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) argument
32 #define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) argument
37 #define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) argument
38 #define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) argument
43 #define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2) argument
44 #define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2) argument
49 #define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE) argument
50 #define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE) argument
72 #define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START) argument
73 #define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_STAR… argument
[all …]
H A Dsb1250_ldt.h58 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
60 #endif /* 1250 PASS2 || 112x PASS1 */
72 #define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_VENDOR) argument
73 #define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_VENDOR, M_LDT_DEVICEID_VENDOR) argument
77 #define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_DEVICEID) argument
78 #define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_DEVICEID, M_LDT_DEVICEID_DEVIC… argument
89 #define M_LDT_CMD_MEMWRINV_EN _SB_MAKEMASK1_32(4)
102 #define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_REV) argument
103 #define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_REV, M_LDT_CLASSREV_REV) argument
107 #define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_CLASS) argument
[all …]
/linux/include/math-emu/
H A Dquad.h33 #define _FP_FRACTBITS_Q (4*_FP_W_TYPE_SIZE)
79 #define FP_DECL_Q(X) _FP_DECL(4,X) argument
80 #define FP_UNPACK_RAW_Q(X,val) _FP_UNPACK_RAW_4(Q,X,val) argument
81 #define FP_UNPACK_RAW_QP(X,val) _FP_UNPACK_RAW_4_P(Q,X,val) argument
82 #define FP_PACK_RAW_Q(val,X) _FP_PACK_RAW_4(Q,val,X) argument
83 #define FP_PACK_RAW_QP(val,X) \ argument
86 _FP_PACK_RAW_4_P(Q,val,X); \
89 #define FP_UNPACK_Q(X,val) \ argument
91 _FP_UNPACK_RAW_4(Q,X,val); \
92 _FP_UNPACK_CANONICAL(Q,4,X); \
[all …]
/linux/drivers/net/phy/mscc/
H A Dmscc_ptp.h16 #define BIU_BLK_ID(x) ((x) << 11) argument
17 #define BIU_CSR_ADDR(x) (x) argument
36 #define ANA_ETH1_NTX_PROT_SIG_OFF(x) (((x) << 16) & ANA_ETH1_NTX_PROT_SIG_OFF_MASK) argument
54 #define ANA_ETH1_NTX_PROT_VLAN_TPID(x) (((x) << 16) & ANA_ETH1_NTX_PROT_VLAN_TPID_MASK) argument
59 #define PTP_ANA_EGR_ENCAP_FLOW_MODE(x) (((x) << 20) & PTP_ANA_EGR_ENCAP_FLOW_MODE_MASK) argument
61 #define PTP_ANA_INGR_ENCAP_FLOW_MODE(x) (((x) << 16) & PTP_ANA_INGR_ENCAP_FLOW_MODE_MASK) argument
62 #define PTP_ANALYZER_MODE_EGR_ENA_MASK GENMASK(6, 4)
63 #define PTP_ANALYZER_MODE_EGR_ENA(x) (((x) << 4) & PTP_ANALYZER_MODE_EGR_ENA_MASK) argument
65 #define PTP_ANALYZER_MODE_INGR_ENA(x) ((x) & PTP_ANALYZER_MODE_INGR_ENA_MASK) argument
77 #define ANA_ETH1_NXT_PROT_ETYPE_MATCH(x) ((x) & ANA_ETH1_NXT_PROT_ETYPE_MATCH_MASK) argument
[all …]
/linux/lib/crypto/
H A Dchacha.c18 u32 *x = state->x; in chacha_permute()
25 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 16); in chacha_permute()
26 x[1] += x[ in chacha_permute()
16 chacha_permute(u32 * x,int nrounds) chacha_permute() argument
78 u32 x[16]; chacha_block_generic() local
105 u32 x[16]; hchacha_block_generic() local
[all...]
/linux/drivers/gpu/drm/radeon/
H A Dni_reg.h30 # define NI_GRPH_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 0) argument
35 # define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4) argument
38 # define NI_GRPH_PRESCALE_BYPASS (1 << 4)
41 # define NI_OVL_PRESCALE_BYPASS (1 << 4)
44 # define NI_INPUT_CSC_GRPH_MODE(x) (((x) & 0x3) << 0) argument
48 # define NI_INPUT_CSC_OVL_MODE(x) (((x) & 0x3) << 4) argument
51 # define NI_OUTPUT_CSC_GRPH_MODE(x) (((x) & 0x7) << 0) argument
56 # define NI_OUTPUT_CSC_PROG_COEFF 4
58 # define NI_OUTPUT_CSC_OVL_MODE(x) (((x) & 0x7) << 4) argument
61 # define NI_GRPH_DEGAMMA_MODE(x) (((x) & 0x3) << 0) argument
[all …]
H A Dcik_reg.h36 # define CIK_GRPH_DEPTH(x) (((x) & 0x3) << 0) argument
40 # define CIK_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) argument
45 # define CIK_GRPH_Z(x) (((x) & 0x3) << 4) argument
46 # define CIK_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) argument
51 # define CIK_GRPH_FORMAT(x) (((x) & 0x7) << 8) argument
59 # define CIK_GRPH_FORMAT_MONO16 4
66 # define CIK_GRPH_FORMAT_BGRA1010102 4
70 # define CIK_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) argument
75 # define CIK_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) argument
80 # define CIK_ADDR_SURF_TILE_SPLIT_1KB 4
[all …]
/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_fwif_sf.h65 #define ROGUE_FW_SF_GID(x) (((u32)(x) >> 12) & 0xfU) argument
67 #define ROGUE_FW_SF_PARAMNUM(x) (((u32)(x) >> 16) & 0xfU) argument
80 "Kick 3D: FWCtx 0x%08.8x @ %d, RTD 0x%08x. Partial render:%d, CSW resume:%d, prio:%d" },
82 "3D finished, HWRTData0State=%x, HWRTData1State=%x" },
83 { ROGUE_FW_LOG_CREATESFID(3, ROGUE_FW_GROUP_MAIN, 4),
84 "Kick 3D TQ: FWCtx 0x%08.8x @ %d, CSW resume:%d, prio: %d" },
85 { ROGUE_FW_LOG_CREATESFID(4, ROGUE_FW_GROUP_MAIN, 0),
88 "Kick Compute: FWCtx 0x%08.8x @ %d, prio: %d" },
92 … "Kick TA: FWCtx 0x%08.8x @ %d, RTD 0x%08x. First kick:%d, Last kick:%d, CSW resume:%d, prio:%d" },
100 "Out of memory! Context 0x%08x, HWRTData 0x%x" },
[all …]
/linux/Documentation/input/devices/
H A Dsentelic.rst12 Finger Sensing Pad Intellimouse Mode (scrolling wheel, 4th and 5th buttons)
15 A) MSID 4: Scrolling wheel mode plus Forward page(4th button) and Backward
21 4. Issuing the "Get device ID" command (0xF2) and waits for the response;
27 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
29 1 |Y|X|y|x|1|M|R|L| 2 |X|X|X|X|X|X|X|X| 3 |Y|Y|Y|Y|Y|Y|Y|Y| 4 | | |B|F|W|W|W|W|
33 Bit6 => X overflow
35 Bit4 => X sign bit
40 Byte 2: X Movement(9-bit 2's complement integers)
42 Byte 4: Bit3~Bit0 => the scrolling wheel's movement since the last data report.
44 Bit4 => 1 = 4th mouse button is pressed, Forward one page.
[all …]
/linux/drivers/scsi/qla2xxx/
H A Dqla_devtbl.h8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
18 "QLA2342", "Sun 133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10a */
20 "QLA2350", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x10c */
21 "QLA2352", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10d */
22 "QLA2352", "Sun 133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10e */
29 "QLA2360", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x115 */
[all …]
/linux/drivers/net/ethernet/freescale/
H A Dgianfar.h87 #define DEFAULT_LFC_PTVVAL 4
230 #define mk_ic_icft(x) \ argument
231 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
233 #define mk_ic_ictt(x) (x&IC_ICTT_MASK) argument
264 #define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK) argument
370 #define ATTRELI_EL(x) (x << 16) argument
372 #define ATTRELI_EI(x) (x) argument
579 u8 l4os; /* Level 4 Header Offset */
600 u8 pro; /* Layer 4 Protocol */
613 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
[all …]
/linux/drivers/gpu/drm/exynos/
H A Dregs-gsc.h26 #define GSC_ENABLE_ON_CLEAR_MASK (1 << 4)
27 #define GSC_ENABLE_ON_CLEAR_ONESHOT (1 << 4)
55 #define GSC_IN_ROT_90 (4 << 16)
75 #define GSC_IN_YUV422_1P (4 << 8)
78 #define GSC_IN_TILE_TYPE_MASK (1 << 4)
79 #define GSC_IN_TILE_C_16x8 (0 << 4)
80 #define GSC_IN_TILE_C_16x16 (1 << 4)
94 #define GSC_SRCIMG_HEIGHT(x) ((x) << 16) argument
96 #define GSC_SRCIMG_WIDTH(x) ((x) << 0) argument
101 #define GSC_SRCIMG_OFFSET_Y(x) ((x) << 16) argument
[all …]
/linux/drivers/net/ethernet/mscc/
H A Docelot_qs.h20 #define XTR_VALID_BYTES(x) (4 - (((x) >> 24) & 3)) argument
24 #define QS_XTR_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2)) argument
26 #define QS_XTR_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2) argument
34 #define QS_XTR_CFG_DP_WM(x) (((x) << 5) & GENMASK(7, 5)) argument
36 #define QS_XTR_CFG_DP_WM_X(x) (((x) & GENMASK(7, 5)) >> 5) argument
37 #define QS_XTR_CFG_SCH_WM(x) (((x) << 2) & GENMASK(4, 2)) argument
38 #define QS_XTR_CFG_SCH_WM_M GENMASK(4, 2)
39 #define QS_XTR_CFG_SCH_WM_X(x) (((x) & GENMASK(4, 2)) >> 2) argument
40 #define QS_XTR_CFG_OFLW_ERR_STICKY(x) ((x) & GENMASK(1, 0)) argument
45 #define QS_INJ_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2)) argument
[all …]
/linux/arch/csky/include/asm/
H A Duaccess.h11 #define __put_user_asm_b(x, ptr, err) \ argument
24 : "=r"(err), "=r"(x), "=r"(ptr), "=r"(errcode) \
25 : "0"(err), "1"(x), "2"(ptr), "3"(-EFAULT) \
29 #define __put_user_asm_h(x, ptr, err) \ argument
42 : "=r"(err), "=r"(x), "=r"(ptr), "=r"(errcode) \
43 : "0"(err), "1"(x), "2"(ptr), "3"(-EFAULT) \
47 #define __put_user_asm_w(x, ptr, err) \ argument
60 : "=r"(err), "=r"(x), "=r"(ptr), "=r"(errcode) \
61 : "0"(err), "1"(x), "2"(ptr), "3"(-EFAULT) \
65 #define __put_user_asm_64(x, ptr, err) \ argument
[all …]
/linux/fs/bcachefs/
H A Dbcachefs_format.h157 __aligned(4)
195 __aligned(4)
391 x(deleted, 0, 0) \
392 x(whiteout, 1, 0) \
393 x(error, 2, 0) \
394 x(cookie, 3, 0) \
395 x(hash_whiteout, 4, BKEY_TYPE_strict_btree_checks) \
396 x(btree_ptr, 5, BKEY_TYPE_strict_btree_checks) \
397 x(extent, 6, BKEY_TYPE_strict_btree_checks) \
398 x(reservation, 7, BKEY_TYPE_strict_btree_checks) \
[all …]
/linux/drivers/gpu/drm/arm/display/komeda/d71/
H A Dd71_regs.h36 #define BLOCK_INFO_N_SUBBLKS(x) ((x) & 0x000F) argument
37 #define BLOCK_INFO_BLK_ID(x) (((x) & 0x00F0) >> 4) argument
38 #define BLOCK_INFO_BLK_TYPE(x) (((x) & 0xFF00) >> 8) argument
39 #define BLOCK_INFO_INPUT_ID(x) ((x) & 0xFFF0) argument
40 #define BLOCK_INFO_TYPE_ID(x) (((x) & 0x0FF0) >> 4) argument
42 #define PIPELINE_INFO_N_OUTPUTS(x) ((x) & 0x000F) argument
43 #define PIPELINE_INFO_N_VALID_INPUTS(x) (((x) & 0x0F00) >> 8) argument
60 #define AD_TH BIT(4)
72 #define GCU_CONTROL_MODE(x) ((x) & 0x7) argument
80 #define GCU_MAX_LINE_SIZE(x) ((x) & 0xFFFF) argument
[all …]
/linux/sound/soc/sof/xtensa/
H A Dcore.c23 * From 4.4.1.5 table 4-64 Exception Causes of Xtensa
33 {4, "Level1InterruptCause",
74 "Coprocessor 4 instruction when cp4 disabled"},
99 "EXCCAUSE 0x%8.8x EXCVADDR 0x%8.8x PS 0x%8.8x SAR 0x%8.8x\n", in xtensa_dsp_oops()
102 "EPC1 0x%8.8x EPC2 0x%8.8x EPC3 0x%8.8x EPC4 0x%8.8x", in xtensa_dsp_oops()
105 "EPC5 0x%8.8x EPC6 0x%8.8x EPC7 0x%8.8x DEPC 0x%8.8x", in xtensa_dsp_oops()
108 "EPS2 0x%8.8x EPS3 0x%8.8x EPS4 0x%8.8x EPS5 0x%8.8x", in xtensa_dsp_oops()
111 "EPS6 0x%8.8x EPS7 0x%8.8x INTENABL 0x%8.8x INTERRU 0x%8.8x", in xtensa_dsp_oops()
120 /* 4 * 8chars + 3 ws + 1 terminating NUL */ in xtensa_stack()
121 unsigned char buf[4 * 8 + 3 + 1]; in xtensa_stack()
[all …]
/linux/drivers/comedi/drivers/
H A Dni_stc.h56 #define NISTC_INTB_ACK_AO_BC_TC_ERR BIT(4)
70 #define NISTC_AI_CMD2_REG 4
78 #define NISTC_AI_CMD2_SC_SW_ON_TC BIT(4)
85 #define NISTC_AO_CMD2_END_ON_BC_TC(x) (((x) & 0x3) << 14) argument
95 #define NISTC_AO_CMD2_BC_SW_ON_TC BIT(4)
115 #define NISTC_AI_CMD1_SCAN_IN_PROG_PULSE BIT(4)
133 #define NISTC_AO_CMD1_DAC1_UPDATE_MODE BIT(4)
140 #define NISTC_DIO_OUT_SERIAL(x) (((x) & 0xff) << 8) argument
142 #define NISTC_DIO_OUT_PARALLEL(x) ((x) & 0xff) argument
144 #define NISTC_DIO_SDIN BIT(4)
[all …]
/linux/sound/soc/codecs/
H A Dtlv320dac33.h96 #define DAC33_PDNALLB (0x01 << 4)
103 #define DAC33_ADJSTEP(x) (x << 0) argument
104 #define DAC33_ADJTHRSHLD(x) (x << 4) argument
107 #define DAC33_REFDIV(x) (x << 4) argument
123 #define DAC33_WLEN_MASK (0x03 << 4)
124 #define DAC33_WLEN_16 (0x00 << 4)
125 #define DAC33_WLEN_20 (0x01 << 4)
126 #define DAC33_WLEN_24 (0x02 << 4)
127 #define DAC33_WLEN_32 (0x03 << 4)
136 #define DAC33_DATA_DELAY(x) (x << 2) argument
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