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/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
[all …]
/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
104 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
105 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
106 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
107 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dipq9574-rdp-common.dtsi97 * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
102 * corner parts to operate at 800MHz
220 * (48 MHZ or 96 MHZ used for different RDP type board). This setting
222 * clock output from WiFi to the CMN PLL is 48 MHZ.
230 * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed
231 * from WiFi output clock 48 MHZ divided by 2.
/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi195 * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz
205 * The 2.4 MHz TIMCLK reference clock is active at
206 * boot time, this is actually the MXTALCLK @19.2 MHz
218 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
241 /* PLL2 is usually 864 MHz and divided into a few fixed rates */
270 clk48: clk48@48M {
298 hclkdma0: hclkdma0@48M {
304 hclksmc: hclksmc@48M {
310 hclksdram: hclksdram@48M {
316 hclkdma1: hclkdma1@48M {
[all …]
/linux/drivers/ata/
H A Dpata_sc1200.c40 * in use. We return 0 for 33MHz 1 for 48MHz and 2 for 66Mhz
51 return 0; /* 33 MHz mode */ in sc1200_clock()
54 0/3 is 33Mhz 1 is 48 2 is 66 */ in sc1200_clock()
75 /* format0, 33Mhz */ in sc1200_set_piomode()
77 /* format1, 33Mhz */ in sc1200_set_piomode()
79 /* format1, 48Mhz */ in sc1200_set_piomode()
81 /* format1, 66Mhz */ in sc1200_set_piomode()
H A Dpata_hpt37x.c124 48,
135 48,
190 48,
595 * @freq: Reported frequency in MHz
598 * and 3 for 66Mhz)
604 return 0; /* 33Mhz slot */ in hpt37x_clock_slot()
606 return 1; /* 40Mhz slot */ in hpt37x_clock_slot()
608 return 2; /* 50Mhz slot */ in hpt37x_clock_slot()
609 return 3; /* 60Mhz slot */ in hpt37x_clock_slot()
688 freq = (fcnt * base) / 192; /* in MHz */ in hpt37x_pci_clock()
[all …]
/linux/drivers/media/i2c/cx25840/
H A Dcx25840-audio.c17 * NTSC Color subcarrier freq * 8 = 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
26 * ref_freq = 28.636360 MHz
28 * ref_freq = 28.636363 MHz
46 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
47 * 432 MHz pre-postdivide in cx25840_set_audclk_freq()
53 * 196.6 MHz pre-postdivide in cx25840_set_audclk_freq()
54 * FIXME < 200 MHz is out of specified valid range in cx25840_set_audclk_freq()
84 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
85 * 432 MHz pre-postdivide in cx25840_set_audclk_freq()
91 * 271 MHz pre-postdivide in cx25840_set_audclk_freq()
[all …]
/linux/drivers/media/tuners/
H A Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/linux/arch/arm/mach-omap1/
H A Dclock_data.c360 * XXX The enable_bit here is misused - it simply switches between 12MHz
361 * and 48MHz. Reimplement with clk_mux.
377 * XXX The enable_bit here is misused - it simply switches between 12MHz
378 * and 48MHz. Reimplement with clk_mux.
396 * XXX The enable_bit here is misused - it simply switches between 12MHz
397 * and 48MHz. Reimplement with clk_mux.
413 * XXX The enable_bit here is misused - it simply switches between 12MHz
414 * and 48MHz. Reimplement with clk_mux.
430 * XXX The enable_bit here is misused - it simply switches between 12MHz
431 * and 48MHz. Reimplement with clk_mux.
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dst,stm32mp21-rcc.yaml36 - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)
37 - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)
38 - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
85 - description: CK_SCMI_FLEXGEN_48 flexgen clock 48
H A Dst,stm32mp25-rcc.yaml36 - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)
37 - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)
38 - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
91 - description: CK_SCMI_FLEXGEN_48 flexgen clock 48
/linux/Documentation/devicetree/bindings/mips/cavium/
H A Ductl.txt29 /* 12MHz, 24MHz and 48MHz allowed */
/linux/drivers/usb/host/
H A Docteon-hcd.h846 * Selects either 480-MHz or 48-MHz (low-power) PHY mode. In
847 * FS and LS modes, the PHY can usually operate on a 48-MHz
849 * * 1'b0: 480-MHz Internal PLL clock
850 * * 1'b1: 48-MHz External Clock
851 * In 480 MHz mode, the UTMI interface operates at either 60 or
852 * 30-MHz, depending upon whether 8- or 16-bit data width is
853 * selected. In 48-MHz mode, the UTMI interface operates at 48
854 * MHz in FS mode and at either 48 or 6 MHz in LS mode
891 * * One 30-MHz PHY clock = 16 bit times
892 * * One 60-MHz PHY clock = 8 bit times
[all …]
/linux/drivers/usb/renesas_usbhs/
H A Drza.c32 /* Select 12MHz XTAL */ in usbhs_rza1_hardware_init()
35 dev_err(usbhs_priv_to_dev(priv), "A 48MHz USB clock or 12MHz main clock is required.\n"); in usbhs_rza1_hardware_init()
/linux/drivers/clk/
H A Dclk-nspire.c13 #define MHZ (1000 * 1000) macro
44 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
46 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
55 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
57 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
132 info.base_clock / MHZ, in nspire_clk_setup()
133 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
134 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_afmt.c33 /* 32kHz 44.1kHz 48kHz */
35 { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
36 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
37 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
38 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
39 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
40 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
41 { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
42 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
43 { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
[all …]
/linux/arch/powerpc/platforms/52xx/
H A Dlite5200.c67 /* Use internal 48 Mhz */ in lite5200_fix_clock_config()
70 if (in_be32(&cdm->rstcfg) & 0x40) /* Assumes 33Mhz clock */ in lite5200_fix_clock_config()
105 port_config &= ~0x00800000; /* 48Mhz internal, pin is GPIO */ in lite5200_fix_port_config()
/linux/Documentation/arch/m68k/
H A Dbuddha-driver.rst32 $48, while it doesn't matter how often you're writing to $4a
33 as long as $48 is not touched. After $48 has been written,
35 address just written. Make sure $4a is written before $48,
144 (exactly 70,5 at 14,18 Mhz on PAL systems).
189 Mhz (for example the NTSC-frequency 28,63636 Mhz), each
/linux/arch/arm/mach-s3c/
H A Dsetup-usb-phy-s3c64xx.c36 case 12 * MHZ: in s3c_usb_otgphy_init()
39 case 24 * MHZ: in s3c_usb_otgphy_init()
43 case 48 * MHZ: in s3c_usb_otgphy_init()
/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dda8xx-cfgchip.txt18 This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
19 clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock.
/linux/drivers/clk/pxa/
H A Dclk-pxa3xx.c25 #define MHz (1000 * 1000) macro
94 #define CKEN_MINI_IM 48 /* < Mini-IM */
183 * standard 24.576MHz. in clk_pxa3xx_ac97_get_rate()
199 return (parent_rate / 48) * smcfs_mult[(acsr >> 23) & 0x7] / in clk_pxa3xx_smemc_get_rate()
242 PXA3XX_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 6, 1, 48, 0),
243 PXA3XX_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 6, 1, 48, 0),
293 return parent_rate / 48 * hss_mult[hss]; in clk_pxa3xx_system_bus_get_rate()
379 13 * MHz); in pxa3xx_register_plls()
386 120 * MHz); in pxa3xx_register_plls()
388 clk_register_fixed_factor(NULL, "spll_624mhz", "osc_13mhz", 0, 48, 1); in pxa3xx_register_plls()
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dpub.h38 #define BRCMS_10_MHZ 10 /* 10Mhz nphy channel bandwidth */
39 #define BRCMS_20_MHZ 20 /* 20Mhz nphy channel bandwidth */
40 #define BRCMS_40_MHZ 40 /* 40Mhz nphy channel bandwidth */
224 * Extended Rateset: 6, 9, 12, 48
229 * Extended Rateset: 6b, 9, 12b, 48
234 * Extended Rateset: 6, 9, 12, 48
238 * Rateset: 1b, 2b, 5.5b, 6b, 9, 11b, 12b, 18, 24b, 36, 48, 54
243 * Extended Rateset: 6, 9, 12, 18, 24, 36, 48, 54
/linux/arch/arm/boot/dts/nspire/
H A Dnspire.dtsi110 * 48 for the display so likely the frequency to the
111 * display is 1MHz and the CLCDCLK is 48 MHz.
/linux/drivers/ssb/
H A Dmain.c858 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ in ssb_calc_clock_rate()
859 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ in ssb_calc_clock_rate()
860 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ in ssb_calc_clock_rate()
861 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ in ssb_calc_clock_rate()
865 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */ in ssb_calc_clock_rate()
871 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */ in ssb_calc_clock_rate()
878 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ in ssb_calc_clock_rate()
879 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ in ssb_calc_clock_rate()
894 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ in ssb_calc_clock_rate()
895 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ in ssb_calc_clock_rate()
[all …]
/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-wpcm450.dtsi33 clk24m: clock-24mhz {
34 /* 24 MHz dummy clock */
40 refclk: clock-48mhz {
41 /* 48 MHz reference oscillator */

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