Lines Matching +full:48 +full:mhz

360  * XXX The enable_bit here is misused - it simply switches between 12MHz
361  * and 48MHz.  Reimplement with clk_mux.
377  * XXX The enable_bit here is misused - it simply switches between 12MHz
378  * and 48MHz.  Reimplement with clk_mux.
396  * XXX The enable_bit here is misused - it simply switches between 12MHz
397  * and 48MHz.  Reimplement with clk_mux.
413  * XXX The enable_bit here is misused - it simply switches between 12MHz
414  * and 48MHz.  Reimplement with clk_mux.
430  * XXX The enable_bit here is misused - it simply switches between 12MHz
431  * and 48MHz.  Reimplement with clk_mux.
448 static struct omap1_clk usb_clko = {	/* 6 MHz output on W4_USB_CLKO */
462 	.rate		= 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
686 	pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",  in omap1_show_rates()