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/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10_mercury_aa1.dtsi42 txd0-skew-ps = <0>; /* -420ps */
43 txd1-skew-ps = <0>; /* -420ps */
44 txd2-skew-ps = <0>; /* -420ps */
45 txd3-skew-ps = <0>; /* -420ps */
46 rxd0-skew-ps = <420>; /* 0ps */
47 rxd1-skew-ps = <420>; /* 0ps */
48 rxd2-skew-ps = <420>; /* 0ps */
49 rxd3-skew-ps = <420>; /* 0ps */
50 txen-skew-ps = <0>; /* -420ps */
52 rxdv-skew-ps = <420>; /* 0ps */
H A Dsocfpga_cyclone5_de0_nano_soc.dts48 txd0-skew-ps = <0>; /* -420ps */
49 txd1-skew-ps = <0>; /* -420ps */
50 txd2-skew-ps = <0>; /* -420ps */
51 txd3-skew-ps = <0>; /* -420ps */
52 rxd0-skew-ps = <420>; /* 0ps */
53 rxd1-skew-ps = <420>; /* 0ps */
54 rxd2-skew-ps = <420>; /* 0ps */
55 rxd3-skew-ps = <420>; /* 0ps */
56 txen-skew-ps = <0>; /* -420ps */
58 rxdv-skew-ps = <420>; /* 0ps */
H A Dsocfpga_arria10_socdk.dtsi81 txd0-skew-ps = <0>; /* -420ps */
82 txd1-skew-ps = <0>; /* -420ps */
83 txd2-skew-ps = <0>; /* -420ps */
84 txd3-skew-ps = <0>; /* -420ps */
85 rxd0-skew-ps = <420>; /* 0ps */
86 rxd1-skew-ps = <420>; /* 0ps */
87 rxd2-skew-ps = <420>; /* 0ps */
88 rxd3-skew-ps = <420>; /* 0ps */
89 txen-skew-ps = <0>; /* -420ps */
91 rxdv-skew-ps = <420>; /* 0ps */
H A Dsocfpga_cyclone5_de10nano.dts47 rxd0-skew-ps = <420>;
48 rxd1-skew-ps = <420>;
49 rxd2-skew-ps = <420>;
50 rxd3-skew-ps = <420>;
52 rxdv-skew-ps = <420>;
/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex_socdk_nand.dts65 txd0-skew-ps = <0>; /* -420ps */
66 txd1-skew-ps = <0>; /* -420ps */
67 txd2-skew-ps = <0>; /* -420ps */
68 txd3-skew-ps = <0>; /* -420ps */
69 rxd0-skew-ps = <420>; /* 0ps */
70 rxd1-skew-ps = <420>; /* 0ps */
71 rxd2-skew-ps = <420>; /* 0ps */
72 rxd3-skew-ps = <420>; /* 0ps */
73 txen-skew-ps = <0>; /* -420ps */
75 rxdv-skew-ps = <420>; /* 0ps */
H A Dsocfpga_n5x_socdk.dts55 txd0-skew-ps = <0>; /* -420ps */
56 txd1-skew-ps = <0>; /* -420ps */
57 txd2-skew-ps = <0>; /* -420ps */
58 txd3-skew-ps = <0>; /* -420ps */
59 rxd0-skew-ps = <420>; /* 0ps */
60 rxd1-skew-ps = <420>; /* 0ps */
61 rxd2-skew-ps = <420>; /* 0ps */
62 rxd3-skew-ps = <420>; /* 0ps */
63 txen-skew-ps = <0>; /* -420ps */
65 rxdv-skew-ps = <420>; /* 0ps */
H A Dsocfpga_agilex_socdk.dts65 txd0-skew-ps = <0>; /* -420ps */
66 txd1-skew-ps = <0>; /* -420ps */
67 txd2-skew-ps = <0>; /* -420ps */
68 txd3-skew-ps = <0>; /* -420ps */
69 rxd0-skew-ps = <420>; /* 0ps */
70 rxd1-skew-ps = <420>; /* 0ps */
71 rxd2-skew-ps = <420>; /* 0ps */
72 rxd3-skew-ps = <420>; /* 0ps */
73 txen-skew-ps = <0>; /* -420ps */
75 rxdv-skew-ps = <420>; /* 0ps */
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10_socdk_nand.dts86 txd0-skew-ps = <0>; /* -420ps */
87 txd1-skew-ps = <0>; /* -420ps */
88 txd2-skew-ps = <0>; /* -420ps */
89 txd3-skew-ps = <0>; /* -420ps */
90 rxd0-skew-ps = <420>; /* 0ps */
91 rxd1-skew-ps = <420>; /* 0ps */
92 rxd2-skew-ps = <420>; /* 0ps */
93 rxd3-skew-ps = <420>; /* 0ps */
94 txen-skew-ps = <0>; /* -420ps */
96 rxdv-skew-ps = <420>; /* 0ps */
H A Dsocfpga_stratix10_socdk.dts102 txd0-skew-ps = <0>; /* -420ps */
103 txd1-skew-ps = <0>; /* -420ps */
104 txd2-skew-ps = <0>; /* -420ps */
105 txd3-skew-ps = <0>; /* -420ps */
106 rxd0-skew-ps = <420>; /* 0ps */
107 rxd1-skew-ps = <420>; /* 0ps */
108 rxd2-skew-ps = <420>; /* 0ps */
109 rxd3-skew-ps = <420>; /* 0ps */
110 txen-skew-ps = <0>; /* -420ps */
112 rxdv-skew-ps = <420>; /* 0ps */
/linux/drivers/regulator/
H A Dcpcap-regulator.c350 0x87, 0x30, 0x3, 0, 420),
356 0x87, 0x30, 0x3, 0, 420),
359 0x87, 0x30, 0x82, 0, 420),
362 0x80, 0xf, 0x80, 0, 420),
368 0x87, 0x38, 0x82, 0, 420),
371 0x43, 0x18, 0x2, 0, 420),
380 0x23, 0x8, 0, 0, 420),
383 0x47, 0x10, 0, 0, 420),
386 0x20c, 0xc0, 0x20c, 0, 420),
389 0x23, 0x8, 0x3, 0, 420),
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32mp15xx-dhcor-testbench.dtsi98 rxd0-skew-ps = <420>;
99 rxd1-skew-ps = <420>;
100 rxd2-skew-ps = <420>;
101 rxd3-skew-ps = <420>;
105 txd0-skew-ps = <420>;
106 txd1-skew-ps = <420>;
107 txd2-skew-ps = <420>;
108 txd3-skew-ps = <420>;
H A Dstm32mp15xx-dhcor-drc-compact.dtsi114 rxd0-skew-ps = <420>;
115 rxd1-skew-ps = <420>;
116 rxd2-skew-ps = <420>;
117 rxd3-skew-ps = <420>;
121 txd0-skew-ps = <420>;
122 txd1-skew-ps = <420>;
123 txd2-skew-ps = <420>;
124 txd3-skew-ps = <420>;
H A Dstm32mp15xx-dhcor-avenger96.dtsi188 rxd0-skew-ps = <420>;
189 rxd1-skew-ps = <420>;
190 rxd2-skew-ps = <420>;
191 rxd3-skew-ps = <420>;
195 txd0-skew-ps = <420>;
196 txd1-skew-ps = <420>;
197 txd2-skew-ps = <420>;
198 txd3-skew-ps = <420>;
/linux/Documentation/gpu/
H A Dafbc.rst82 420), can be encoded into one, or multiple, AFBC planes. As with
208 - 8-bit per component YCbCr 420, single plane
215 - 10-bit per component YCbCr 420, single plane
222 - 8-bit per component YCbCr 420, two plane
230 - 10-bit per component YCbCr 420, two plane
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-fw-isys.h173 IPU6_FW_ISYS_FRAME_FORMAT_NV12, /* 12 bit YUV 420, Y, UV plane */
174 IPU6_FW_ISYS_FRAME_FORMAT_NV12_16, /* 16 bit YUV 420, Y, UV plane */
175 /* 12 bit YUV 420, Intel proprietary tiled format */
179 IPU6_FW_ISYS_FRAME_FORMAT_NV21, /* 12 bit YUV 420, Y, VU plane */
181 IPU6_FW_ISYS_FRAME_FORMAT_YV12, /* 12 bit YUV 420, Y, V, U plane */
183 IPU6_FW_ISYS_FRAME_FORMAT_YUV420, /* 12 bit YUV 420, Y, U, V plane */
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn32/
H A Ddcn32_dpp.c69 /* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */ in dscl32_calc_lb_num_partitions()
75 /* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */ in dscl32_calc_lb_num_partitions()
202 /* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */ in dscl32_spl_calc_lb_num_partitions()
208 /* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */ in dscl32_spl_calc_lb_num_partitions()
/linux/drivers/gpu/drm/amd/display/dc/dml/dsc/
H A Drc_calc_fpu.c67 int mode = MODE_SELECT(444, 422, 420); in get_qp_set()
88 TABLE_CASE(420, 8, max); in get_qp_set()
89 TABLE_CASE(420, 8, min); in get_qp_set()
90 TABLE_CASE(420, 10, max); in get_qp_set()
91 TABLE_CASE(420, 10, min); in get_qp_set()
92 TABLE_CASE(420, 12, max); in get_qp_set()
93 TABLE_CASE(420, 12, min); in get_qp_set()
H A Drc_calc_fpu.h60 CM_420 /* native 420 */
/linux/drivers/gpu/drm/armada/
H A Darmada_fb.c51 FMT(YUV420, 420, CFG_YUV2RGB); in armada_framebuffer_create()
52 FMT(YVU420, 420, CFG_YUV2RGB | CFG_SWAPUV); in armada_framebuffer_create()
/linux/sound/firewire/
H A DKconfig59 * Mackie(Loud) U.420/U.420d
/linux/sound/firewire/oxfw/
H A Doxfw.c53 "U.420"}; in detect_loud_models()
358 // U.420: Unknown
359 // U.420d: Unknown
/linux/drivers/media/platform/verisilicon/
H A Drockchip_av1_filmgrain.c49 56, -432, 224, -980, 272, -260, 144, -436, 420, 356, 364,
70 -196, 388, 304, 500, 724, -160, 244, -84, 272, -256, -420,
110 -600, 768, 268, -248, -88, -132, -420, -432, 80, -288, 404,
152 -56, 544, 400, -672, -420, 728, 16, 320, 44, -284, -380,
158 -1500, 960, -40, 176, 168, 1516, 420, -504, -344, -364, -360,
183 -232, 420, 4, -344, -464, 556, 244, -416, -32, 252, 0,
/linux/sound/usb/6fire/
H A Dpcm.c24 static const int rates_in_packet_size[] = { 228, 228, 420, 420, 404, 404 };
25 static const int rates_out_packet_size[] = { 228, 228, 420, 420, 604, 604 };
/linux/drivers/gpu/drm/meson/
H A Dmeson_encoder_hdmi.c81 /* For 420, pixel clock is half unlike venc clock */ in meson_encoder_hdmi_set_vclk()
137 /* If sink does not support 540MHz, reject the non-420 HDMI2 modes */ in meson_encoder_hdmi_mode_valid()
157 /* For 420, pixel clock is half unlike venc clock */ in meson_encoder_hdmi_mode_valid()
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dti,iodelay.txt39 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */

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