xref: /linux/Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: TI wrapper module for the Cadence USBSS-DRD controller
8
9maintainers:
10  - Roger Quadros <rogerq@kernel.org>
11
12properties:
13  compatible:
14    oneOf:
15      - const: ti,j721e-usb
16      - items:
17          - const: ti,am64-usb
18          - const: ti,j721e-usb
19
20  reg:
21    maxItems: 1
22
23  ranges: true
24
25  power-domains:
26    description:
27      PM domain provider node and an args specifier containing
28      the USB device id value. See,
29      Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
30    maxItems: 1
31
32  clocks:
33    description: Clock phandles to usb2_refclk and lpm_clk
34    minItems: 2
35    maxItems: 2
36
37  clock-names:
38    items:
39      - const: ref
40      - const: lpm
41
42  ti,usb2-only:
43    description:
44      If present, it restricts the controller to USB2.0 mode of
45      operation. Must be present if USB3 PHY is not available
46      for USB.
47    type: boolean
48
49  ti,vbus-divider:
50    description:
51      Should be present if USB VBUS line is connected to the
52      VBUS pin of the SoC via a 1/3 voltage divider.
53    type: boolean
54
55  '#address-cells':
56    const: 2
57
58  '#size-cells':
59    const: 2
60
61  dma-coherent: true
62
63patternProperties:
64  "^usb@":
65    type: object
66
67required:
68  - compatible
69  - reg
70  - power-domains
71  - clocks
72  - clock-names
73
74additionalProperties: false
75
76examples:
77  - |
78    #include <dt-bindings/soc/ti,sci_pm_domain.h>
79    #include <dt-bindings/interrupt-controller/arm-gic.h>
80
81    bus {
82        #address-cells = <2>;
83        #size-cells = <2>;
84
85        cdns_usb@4104000 {
86            compatible = "ti,j721e-usb";
87            reg = <0x00 0x4104000 0x00 0x100>;
88            power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
89            clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
90            clock-names = "ref", "lpm";
91            assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
92            assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
93            #address-cells = <2>;
94            #size-cells = <2>;
95
96            usb@6000000 {
97                  compatible = "cdns,usb3";
98                  reg = <0x00 0x6000000 0x00 0x10000>,
99                        <0x00 0x6010000 0x00 0x10000>,
100                        <0x00 0x6020000 0x00 0x10000>;
101                  reg-names = "otg", "xhci", "dev";
102                  interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
103                               <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
104                               <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
105                  interrupt-names = "host",
106                                    "peripheral",
107                                    "otg";
108                  maximum-speed = "super-speed";
109                  dr_mode = "otg";
110            };
111        };
112    };
113