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/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa2xx.dtsi58 pxairq: interrupt-controller@40d00000 {
67 gpio: gpio@40e00000 {
80 gcb0: gpio@40e00000 {
84 gcb1: gpio@40e00004 {
88 gcb2: gpio@40e00008 {
91 gcb3: gpio@40e0000c {
98 reg = <0x40100000 0x30>;
106 reg = <0x40200000 0x30>;
114 reg = <0x40700000 0x30>;
122 reg = <0x41600000 0x30>;
[all …]
/linux/drivers/gpu/drm/ci/xfails/
H A Dvkms-none-skips.txt26 # ? asm_exc_page_fault+0x26/0x30
39 # ret_from_fork_asm+0x1a/0x30
77 # ? asm_exc_page_fault+0x26/0x30
90 # ret_from_fork_asm+0x1a/0x30
113 … e8 71 f0 ff ff 4b 8b 04 fc 48 8b 4c 24 50 48 8b 7c 24 40 48 8b 80 48 01 00 00 <48> 63 70 18 8b 40…
128 # ? asm_exc_page_fault+0x26/0x30
141 # ret_from_fork_asm+0x1a/0x30
147 … e8 71 f0 ff ff 4b 8b 04 fc 48 8b 4c 24 50 48 8b 7c 24 40 48 8b 80 48 01 00 00 <48> 63 70 18 8b 40…
164 … e8 71 f0 ff ff 4b 8b 04 fc 48 8b 4c 24 50 48 8b 7c 24 40 48 8b 80 48 01 00 00 <48> 63 70 18 8b 40…
181 # ? asm_exc_page_fault+0x26/0x30
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dmarvell,armada-370-xp-timer.txt31 reg = <0x20300 0x30>, <0x21040 0x30>;
32 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
40 reg = <0x20300 0x30>, <0x21040 0x30>;
41 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt7981.c87 PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1),
88 PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1),
89 PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1),
90 PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1),
91 PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
92 PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1),
93 PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1),
94 PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1),
95 PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1),
96 PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1),
[all …]
H A Dpinctrl-mt7986.c99 PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x30, 0x10, 12, 1),
100 PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1),
101 PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1),
102 PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x30, 0x10, 15, 1),
103 PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x30, 0x10, 19, 1),
104 PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1),
105 PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1),
106 PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1),
112 PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x40, 0x10, 18, 1),
118 PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x30, 0x10, 2, 1),
[all …]
H A Dpinctrl-mt8173.c80 MTK_PIN_IES_SMT_SPEC(40, 41, 0x930, 9),
133 MTK_PIN_IES_SMT_SPEC(40, 41, 0x900, 9),
184 MTK_PIN_DRV_GRP(5, DRV_BASE+0x30, 0, 0),
185 MTK_PIN_DRV_GRP(6, DRV_BASE+0x30, 0, 0),
186 MTK_PIN_DRV_GRP(7, DRV_BASE+0x30, 0, 0),
187 MTK_PIN_DRV_GRP(8, DRV_BASE+0x30, 0, 0),
188 MTK_PIN_DRV_GRP(9, DRV_BASE+0x30, 0, 0),
189 MTK_PIN_DRV_GRP(10, DRV_BASE+0x30, 4, 1),
190 MTK_PIN_DRV_GRP(11, DRV_BASE+0x30, 4, 1),
191 MTK_PIN_DRV_GRP(12, DRV_BASE+0x30, 4, 1),
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-newvision-nv3051d.c57 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30); in panel_nv3051d_init_sequence()
101 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30); in panel_nv3051d_init_sequence()
115 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD7, 0x30); in panel_nv3051d_init_sequence()
140 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30); in panel_nv3051d_init_sequence()
153 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x2A); in panel_nv3051d_init_sequence()
216 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30); in panel_nv3051d_init_sequence()
235 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30); in panel_nv3051d_init_sequence()
444 .hsync_start = 640 + 40,
445 .hsync_end = 640 + 40 + 2,
446 .htotal = 640 + 40 + 2 + 80,
[all …]
H A Dpanel-xinpeng-xpp055c272.c88 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETDISP, 0xc8, 0x12, 0x30); in xpp055c272_init_sequence()
117 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x05, in xpp055c272_init_sequence()
214 .hsync_start = 720 + 40,
215 .hsync_end = 720 + 40 + 10,
216 .htotal = 720 + 40 + 10 + 40,
/linux/arch/arm/boot/dts/ti/omap/
H A Ddm814x-clocks.dtsi9 adpll_mpu_ck: adpll@40 {
24 reg = <0x80 0x30>;
35 reg = <0xb0 0x30>;
46 reg = <0xe0 0x30>;
57 reg = <0x110 0x30>;
68 reg = <0x140 0x30>;
79 reg = <0x170 0x30>;
90 reg = <0x1a0 0x30>;
101 reg = <0x1d0 0x30>;
112 reg = <0x200 0x30>;
[all …]
/linux/arch/sparc/crypto/
H A Dcamellia_asm.S94 stx %o4, [%o1 + 0x30] ! k[12, 13]
105 stx %o4, [%o1 + 0xa0] ! k[40, 41]
136 std %f0, [%o1 + 0x30] ! k[12, 13]
152 stx %o4, [%o1 + 0xa0] ! k[40, 41]
171 ldx [%o1 + 0x30], %o4 ! k[12, 13]
174 stx %o4, [%o1 + 0x30] ! k[12, 13]
213 ldd [%o1 + 0x30], %f2
227 std %f0, [%o3 + 0x30]
262 ldd [%o0 + 0x30], %f16
275 ldd [%o0 + 0x30], %f16
[all …]
H A Daes_asm.S61 ENCRYPT_TWO_ROUNDS_LAST(KEY_BASE + 40, I0, I1, T0, T1)
69 ENCRYPT_TWO_ROUNDS_LAST_2(KEY_BASE + 40, I0, I1, I2, I3, T0, T1, T2, T3)
78 ENCRYPT_TWO_ROUNDS(KEY_BASE + 40, I0, I1, T0, T1) \
95 ENCRYPT_256_TWO_ROUNDS_2(KEY_BASE + 40, I0, I1, I2, I3, KEY_BASE + 0) \
163 DECRYPT_TWO_ROUNDS_LAST(KEY_BASE + 40, I0, I1, T0, T1)
171 DECRYPT_TWO_ROUNDS_LAST_2(KEY_BASE + 40, I0, I1, I2, I3, T0, T1, T2, T3)
180 DECRYPT_TWO_ROUNDS(KEY_BASE + 40, I0, I1, T0, T1) \
197 DECRYPT_256_TWO_ROUNDS_2(KEY_BASE + 40, I0, I1, I2, I3, KEY_BASE + 0) \
257 AES_KEXPAND1(32, 38, 0x4, 40)
258 AES_KEXPAND2(34, 40, 42)
[all …]
/linux/drivers/net/wireless/marvell/mwifiex/
H A Dcfp.c35 0x30, 0x48, 0x60, 0x6c, 0 };
43 0x24, 0x30, 0x48, 0x60, 0x6C, 0x90,
51 0x30, 0x48, 0x60, 0x6c, 0 };
54 0x12, 0x16, 0x18, 0x24, 0x30, 0x48,
57 u16 region_code_index[MWIFIEX_MAX_REGION_CODE] = { 0x00, 0x10, 0x20, 0x30,
66 /* LGI 40M */
70 /* SGI 40M */
101 /* LG 40M */
105 /* SG 40M */
134 /* LG 40M */
[all …]
/linux/drivers/media/dvb-frontends/
H A Dtda18271c2dd_maps.h153 { 164700000, 0x30 },
180 { 194000000, 0x30 },
222 { 282000000, 0x30 },
351 { 580000000, 0x30 },
513 { 165500000, 0x34, 0x30 },
517 { 248500000, 0x30, 0x20 },
553 { 146500000, 0xBC, 0x30 },
705 { 422000000, 0x30 },
735 { 704000000, 0x30 },
780 { 70100000, 0x01, 40 },
[all …]
/linux/drivers/clk/
H A Dclk-loongson2.c140 CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x30, 32, 10, 26, 6),
167 CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x30, 21, 9, 32, 6),
169 CLK_GATE(LOONGSON2_OUT0_GATE, "out0_gate", "pll_0", 0, 40),
172 CLK_GATE(LOONGSON2_DC_GATE, "dc_gate", "pll_1", 0x10, 40),
175 CLK_GATE(LOONGSON2_HDA_GATE, "hda_gate", "pll_2", 0x20, 40),
178 CLK_GATE(LOONGSON2_PIX0_GATE, "pix0_gate", "pll_pix0", 0x30, 40),
179 CLK_GATE(LOONGSON2_PIX1_GATE, "pix1_gate", "pll_pix1", 0x40, 40),
189 CLK_DIV(LOONGSON2_PIX0_CLK, "clk_pix0", "pll_pix0", 0x30, 0, 6),
195 CLK_SCALE(LOONGSON2_DES_CLK, "clk_des", "clk_node", 0x50, 40, 3),
/linux/tools/testing/selftests/kvm/lib/riscv/
H A Dhandlers.S19 sd x6, 40(sp)
43 sd x30, 232(sp)
61 ld x30, 232(sp)
85 ld x6, 40(sp)
/linux/arch/alpha/include/asm/
H A Dcore_marvel.h137 io7_csr IO_ASIC_REV; /* 0x30.0000 */
141 io7_csr PO7_RST2; /* 0x30.0100 */
146 io7_csr IO7_ACC_CLUMP; /* 0x30.0300 */
150 io7_csr IO7_UPH_TO; /* 0x30.0400 */
154 io7_csr PO7_MONCTL; /* 0x30.0500 */
158 io7_csr PO7_SCRATCH; /* 0x30.0600 */
162 io7_csr PO7_PMASK; /* 0x30.0700 */
166 io7_csr PO7_ERROR_SUM; /* 0x30.2000 */
170 io7_csr PO7_UNCRR_SYM; /* 0x30.2100 */
173 io7_csr PO7_UGBGE_SYM; /* 0x30.2200 */
[all …]
/linux/drivers/edac/
H A Damd64_edac.h131 * F15 M30h D18F1x2[4C:40]
258 #define UMCCH_ADDR_MASK_SEC_DDR5 0x30
285 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
351 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
417 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr; in get_dram_base()
427 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim; in get_dram_limit()
437 if (pvt->fam == 0x15 && pvt->model >= 0x30) in dct_sel_interleave_addr()
499 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in dram_intlv_en()
509 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in dhar_valid()
519 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in dct_sel_baseaddr()
/linux/tools/testing/selftests/kvm/lib/
H A Dguest_modes.c34 guest_mode_append(VM_MODE_P40V48_4K, ipa4k >= 40); in guest_modes_append_default()
35 guest_mode_append(VM_MODE_P40V48_16K, ipa16k >= 40); in guest_modes_append_default()
36 guest_mode_append(VM_MODE_P40V48_64K, ipa64k >= 40); in guest_modes_append_default()
43 vm_mode_default = ipa4k >= 40 ? VM_MODE_P40V48_4K : NUM_VM_MODES; in guest_modes_append_default()
70 if (info.ibc >= 0x30) in guest_modes_append_default()
/linux/drivers/gpu/host1x/
H A Ddev.c148 .offset = 0x30,
154 .offset = 0x30,
166 .dma_mask = DMA_BIT_MASK(40),
179 .offset = 0x30,
185 .offset = 0x30,
191 .offset = 0x30,
203 .dma_mask = DMA_BIT_MASK(40),
245 .offset = 0x30,
246 .limit = 0x30
257 .offset = 0x30,
[all …]
/linux/drivers/clk/uniphier/
H A Dclk-uniphier-mio.c17 UNIPHIER_CLK_FACTOR("sd-40m", -1, "sd-200m", 1, 5), \
33 "sd-40m", \
38 .reg = 0x30 + 0x200 * (ch), \
/linux/Documentation/driver-api/media/drivers/
H A Dtuners.rst13 - P= PHILIPS_API (VHF_LO=0xA0, VHF_HI=0x90, UHF=0x30, radio=0x04)
82 40x2: Tuner (5V/33V), TEMIC_API.
83 40x6: Tuner 5V
85 40x9: Tuner+FM compact
97 Note: Only 40x2 series has TEMIC_API, all newer tuners have PHILIPS_API.
/linux/drivers/video/fbdev/sis/
H A Dsis.h90 #define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 65x, 740, 661, 741 */
128 #define DAC2_ADR (0x16-0x30)
129 #define DAC2_DATA (0x17-0x30)
130 #define VB_PART1_ADR (0x04-0x30)
131 #define VB_PART1_DATA (0x05-0x30)
132 #define VB_PART2_ADR (0x10-0x30)
133 #define VB_PART2_DATA (0x11-0x30)
134 #define VB_PART3_ADR (0x12-0x30)
135 #define VB_PART3_DATA (0x13-0x30)
136 #define VB_PART4_ADR (0x14-0x30)
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm7445.dtsi72 serial@40ab00 {
99 irq0_intc: interrupt-controller@40a780 {
127 reg = <0x3e1000 0x30>;
137 reg = <0x410640 0x30>;
200 upg_gio: gpio@40a700 {
/linux/arch/mips/boot/dts/brcm/
H A Dbcm7346.dtsi61 reg = <0x411400 0x30>, <0x411600 0x30>;
72 reg = <0x403000 0x30>;
245 reg = <0x408440 0x30>;
312 compatible = "brcm,40nm-ephy",
396 reg = <0x411000 0x30>;
419 interrupts = <40>;
464 reg = <0x411d00 0x30>;
/linux/samples/hid/
H A Dhid_mouse.bpf.c109 * 0x09, 0x30, // Usage (X) 38 in BPF_PROG()
110 * 0x09, 0x31, // Usage (Y) 40 in BPF_PROG()
117 data[41] = 0x30; in BPF_PROG()

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