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/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
43 SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
44 {"TC58NVG6D2 64G 3.3V 8-bit",
46 SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
47 {"SDTNQGAMA 64G 3.3V 8-bit",
[all …]
/linux/arch/alpha/kernel/
H A Dsys_wildfire.c1 // SPDX-License-Identifier: GPL-2.0
41 int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1); in wildfire_update_irq_hw()
42 int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1); in wildfire_update_irq_hw()
49 " got irq %d for non-existent PCA %d" in wildfire_update_irq_hw()
57 enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */ in wildfire_update_irq_hw()
72 enable0 = (unsigned long *) &pca->pca_int[0].enable; in wildfire_init_irq_hw()
73 enable1 = (unsigned long *) &pca->pca_int[1].enable; in wildfire_init_irq_hw()
74 enable2 = (unsigned long *) &pca->pca_int[2].enable; in wildfire_init_irq_hw()
75 enable3 = (unsigned long *) &pca->pca_int[3].enable; in wildfire_init_irq_hw()
77 target0 = (unsigned long *) &pca->pca_int[0].target; in wildfire_init_irq_hw()
[all …]
/linux/drivers/clocksource/
H A Dtimer-ep93xx.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on a rewrite of arch/arm/mach-ep93xx/timer.c:
14 #include <linux/io-64-nonatomic-lo-hi.h>
26 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
27 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
28 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
29 * is free-running, and can't generate interrupts.
32 * most common values of HZ divide 508 kHz nicely. We pick the 32 bit
38 * a stable 40 bit time base.
45 #define EP93XX_TIMER123_CONTROL_ENABLE BIT(7)
[all …]
/linux/arch/mips/loongson64/
H A Ddma.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/dma-direct.h>
10 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in phys_to_dma()
11 * Loongson-3's 48bit address space and embed it into 40bit */ in phys_to_dma()
19 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in dma_to_phys()
20 * Loongson-3's 48bit address space and embed it into 40bit */ in dma_to_phys()
/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa3xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
19 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \
20 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \
21 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
23 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \
33 (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \
[all …]
/linux/arch/x86/lib/
H A Dcsum-partial_64.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/x86_64/lib/csum-partial.c
6 * in an architecture-specific manner due to speed.
12 #include <asm/word-at-a-time.h>
35 * Returns a 32bit checksum.
41 * checksums on IPv6 headers (40 bytes) and other small parts.
42 * it's best to have buff aligned on a 64-bit boundary
48 /* Do two 40-byte chunks in parallel to get better ILP */ in csum_partial()
53 temp64_2 = update_csum_40b(temp64_2, buff + 40); in csum_partial()
55 len -= 80; in csum_partial()
[all …]
/linux/Documentation/arch/powerpc/
H A Dassociativity.rst9 are represented as being members of a sub-grouping domain. This performance
17 Hypervisor indicates the type/form of associativity used via "ibm,architecture-vec-5 property".
18 Bit 0 of byte 5 in the "ibm,architecture-vec-5" property indicates usage of Form 0 or Form 1.
20 bit 2 of byte 5 in the "ibm,architecture-vec-5" property is used.
23 ------
27 ------
28 With Form 1 a combination of ibm,associativity-reference-points, and ibm,associativity
34 The “ibm,associativity-reference-points” property contains a list of one or more numbers
43 if they belong to the same higher-level domains. For mismatch at every higher
48 -------
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx.h7 * Copyright (c) 2003-2017 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
42 /* These macros for use when using 32 bit pointers. */
56 #include <asm/octeon/cvmx-asm.h>
57 #include <asm/octeon/cvmx-packet.h>
58 #include <asm/octeon/cvmx-sysinfo.h>
60 #include <asm/octeon/cvmx-ciu-defs.h>
61 #include <asm/octeon/cvmx-ciu3-defs.h>
62 #include <asm/octeon/cvmx-gpio-defs.h>
[all …]
/linux/drivers/staging/fbtft/
H A Dfb_hx8353d.c1 // SPDX-License-Identifier: GPL-2.0+
18 #define DEFAULT_GAMMA "50 77 40 08 BF 00 03 0F 00 01 73 00 72 03 B0 0F 08 00 0F"
22 par->fbtftops.reset(par); in init_display()
43 /* SLPOUT - Sleep out & booster on */ in init_display()
47 /* DISPON - Display On */ in init_display()
53 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, in init_display()
56 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, in init_display()
59 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62); in init_display()
76 #define my BIT(7)
77 #define mx BIT(6)
[all …]
/linux/drivers/auxdisplay/
H A Dpanel.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2000-2008, Willy Tarreau <w@1wt.eu>
5 * Copyright (C) 2016-2017 Glider bvba
10 * The LCD module may either be an HD44780-like 8-bit parallel LCD, or a 1-bit
15 * data output pins or to the ground. The combinations have to be hard-coded
22 * - the initialization/deinitialization process is very dirty and should
26 * - document 24 keys keyboard (3 rows of 8 cols, 32 diodes + 2 inputs)
27 * - make the LCD a part of a virtual screen of Vx*Vy
28 * - make the inputs list smp-safe
29 * - change the keyboard to a double mapping : signals -> key_id -> values
[all …]
/linux/sound/soc/codecs/
H A Dmsm8916-wcd-digital.c1 // SPDX-License-Identifier: GPL-2.0
21 #define CLK_RX_RESET_B1_CTL_TX1_RESET_MASK BIT(0)
22 #define CLK_RX_RESET_B1_CTL_TX2_RESET_MASK BIT(1)
30 #define DMIC_B1_CTL_DMIC0_CLK_EN_MASK BIT(0)
31 #define DMIC_B1_CTL_DMIC0_CLK_EN_ENABLE BIT(0)
34 #define RX_I2S_CTL_RX_I2S_MODE_MASK BIT(5)
35 #define RX_I2S_CTL_RX_I2S_MODE_16 BIT(5)
45 #define TX_I2S_CTL_TX_I2S_MODE_MASK BIT(5)
46 #define TX_I2S_CTL_TX_I2S_MODE_16 BIT(5)
61 #define MCLK_CTL_MCLK_EN_MASK BIT(0)
[all …]
/linux/drivers/input/joystick/
H A Dgf2k.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 1998-2001 Vojtech Pavlik
24 #define GF2K_START 400 /* The time we wait for the first bit [400 us] */
25 #define GF2K_STROBE 40 /* The time we wait for the first bit [40 us] */
42 static char gf2k_length[] = { 40, 40, 40, 40, 40, 40, 40, 40 };
43 … char gf2k_hat_to_axis[][2] = {{ 0, 0}, { 0,-1}, { 1,-1}, { 1, 0}, { 1, 1}, { 0, 1}, {-1, 1}, {-1,…
45 static char *gf2k_names[] = {"", "Genius G-09D", "Genius F-30D", "Genius F-30", "Genius MaxFighter …
46 "Genius F-30-5", "Genius Flight2000 F-23", "Genius F-31"};
93 t--; u = v; in gf2k_read_packet()
123 while ((gameport_read(gameport) & 1) && t) t--; in gf2k_trigger_seq()
[all …]
/linux/Documentation/filesystems/ext4/
H A Dinodes.rst1 .. SPDX-License-Identifier: GPL-2.0
4 -----------
11 that file. ext4 appears to cheat (for performance reasons) a little bit
15 links and is in general more seek-happy than ext4 due to its simpler
22 ``(inode_number - 1) / sb.s_inodes_per_group``, and the offset into the
23 group's table is ``(inode_number - 1) % sb.s_inodes_per_group``. There
31 .. list-table::
32 :widths: 8 8 24 40
33 :header-rows: 1
36 * - Offset
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_hw.c1 // SPDX-License-Identifier: GPL-2.0
24 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
26 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
28 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
29 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
34 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
39 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
41 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
43 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
44 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
[all …]
H A Dice_ethtool.h1 /* SPDX-License-Identifier: GPL-2.0-only */
66 * Array index corresponds to HW PHY type bit, see
101 [30] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full),
102 [31] = ICE_PHY_TYPE(40GB, 40000baseSR4_Full),
103 [32] = ICE_PHY_TYPE(40GB, 40000baseLR4_Full),
104 [33] = ICE_PHY_TYPE(40GB, 40000baseKR4_Full),
105 [34] = ICE_PHY_TYPE(40GB, 40000baseSR4_Full),
106 [35] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full),
111 [40] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
138 * Array index corresponds to HW PHY type bit, see
/linux/arch/powerpc/lib/
H A Dchecksum_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains assembly-language implementations
4 * of IP-style 1's complement checksum routines.
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
19 * and adds in "sum" (32-bit).
35 rldicl. r6,r3,64-1,64-2 /* r6 = (r3 >> 1) & 0x3 */
62 stdu r1,-STACKFRAMESIZE(r1)
83 ld r14,40(r3)
110 ld r14,40(r3)
176 rldicl r4,r0,32,0 /* fold two 32 bit halves together */
[all …]
/linux/Documentation/devicetree/bindings/ufs/
H A Dsnps,tc-dwc-g210.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/snps,tc-dwc-g210.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Wei <liwei213@huawei.com>
18 - snps,dwc-ufshcd-1.40a
20 - compatible
23 - $ref: ufs-common.yaml
28 - enum:
29 - snps,g210-tc-6.00-20bit
[all …]
/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include "clk-uniphier.h"
12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
25 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
[all …]
/linux/arch/m68k/fpsp040/
H A Dfpsp.h11 | fpsp.h --- stack frame offsets during FPSP exception handling
18 | link a6,#-LOCAL_SIZE
19 | fsave -(a7)
20 | movem.l d0-d1/a0-a1,USER_DA(a6)
21 | fmovem.x fp0-fp3,USER_FP0(a6)
26 | A7 ---> +-------------------------------+
30 | +-------------------------------+
36 | +-------------------------------+
37 | A6 ---> | Saved A6 |
38 | +-------------------------------+
[all …]
/linux/lib/
H A Dbitmap.c1 // SPDX-License-Identifier: GPL-2.0-only
32 * endian architectures. See the big-endian headers
33 * include/asm-ppc64/bitops.h and include/asm-s390/bitops.h
82 * __bitmap_shift_right - logical right shift of the bits in a bitmap
88 * Shifting right (dividing) means moving bits in the MS -> LS bit
109 if (off + k + 1 == lim - 1) in __bitmap_shift_right()
111 upper <<= (BITS_PER_LONG - rem); in __bitmap_shift_right()
114 if (off + k == lim - 1) in __bitmap_shift_right()
120 memset(&dst[lim - off], 0, off*sizeof(unsigned long)); in __bitmap_shift_right()
126 * __bitmap_shift_left - logical left shift of the bits in a bitmap
[all …]
/linux/drivers/net/ppp/
H A Dppp_mppe.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 #define MPPE_MAX_KEY_LEN 16 /* largest key length (128-bit) */
6 #define MPPE_OPT_40 0x01 /* 40 bit */
7 #define MPPE_OPT_128 0x02 /* 128 bit */
10 #define MPPE_OPT_56 0x08 /* 56 bit */
19 * names above since C and H are the same bit. We could do a u_int32
25 #define MPPE_L_BIT 0x20 /* 40-bit */
26 #define MPPE_S_BIT 0x40 /* 128-bit */
27 #define MPPE_M_BIT 0x80 /* 56-bit, not supported */
30 /* Does not include H bit; used for least significant octet only. */
[all …]
/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_regs.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
3 /* This file is autogenerated by cml-utils 2021-10-10 13:25:08 +0200.
46 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ BIT(16)
61 #define ANA_ADVLEARN_VLAN_CHK BIT(0)
73 #define ANA_ANAINTR_INTR BIT(1)
79 #define ANA_ANAINTR_INTR_ENA BIT(0)
172 #define ANA_PGID_CFG_OBEY_VLAN BIT(0)
179 #define ANA_MACHDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 40, 0, 1, 4)
187 #define ANA_MACACCESS_CHANGE2SW BIT(17)
193 #define ANA_MACACCESS_MAC_CPU_COPY BIT(16)
[all …]
/linux/drivers/edac/
H A Damd64_edac.h5 * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
105 * PCI-defined configuration space registers
119 * Function 1 - Address Map
131 * F15 M30h D18F1x2[4C:40]
135 #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
136 #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
137 #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
140 #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
141 #define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
142 #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dfw.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
16 /* support till 64 bit bus width OS */
19 #define MAX_802_11_HEADER_LENGTH (40 + \
31 #define FW_DIG_ENABLE_CTL BIT(0)
32 #define FW_HIGH_PWR_ENABLE_CTL BIT(1)
33 #define FW_SS_CTL BIT(2)
34 #define FW_RA_INIT_CTL BIT(3)
35 #define FW_RA_BG_CTL BIT(4)
36 #define FW_RA_N_CTL BIT(5)
[all …]
/linux/drivers/soc/fsl/qbman/
H A Dqman_priv.h1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
34 #include <linux/dma-mapping.h>
44 u16 channel_wq; /* ignores wq (3 lsbits): _res[0-2] */
51 return wq->channel_wq >> 3; in qm_mcr_querywq_get_chan()
74 u8 i_bcnt_hi; /* high 8-bits of 40-bit "Instant" */
75 __be32 i_bcnt_lo; /* low 32-bits of 40-bit */
77 u8 a_bcnt_hi; /* high 8-bits of 40-bit "Average" */
78 __be32 a_bcnt_lo; /* low 32-bits of 40-bit */
84 return ((u64)q->i_bcnt_hi << 32) | be32_to_cpu(q->i_bcnt_lo); in qm_mcr_querycgr_i_get64()
88 return ((u64)q->a_bcnt_hi << 32) | be32_to_cpu(q->a_bcnt_lo); in qm_mcr_querycgr_a_get64()
[all …]

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