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/linux/Documentation/core-api/
H A Dpacking.rst6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
[all …]
/linux/arch/alpha/kernel/
H A Dsys_wildfire.c1 // SPDX-License-Identifier: GPL-2.0
41 int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1); in wildfire_update_irq_hw()
42 int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1); in wildfire_update_irq_hw()
49 " got irq %d for non-existent PCA %d" in wildfire_update_irq_hw()
57 enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */ in wildfire_update_irq_hw()
72 enable0 = (unsigned long *) &pca->pca_int[0].enable; in wildfire_init_irq_hw()
73 enable1 = (unsigned long *) &pca->pca_int[1].enable; in wildfire_init_irq_hw()
74 enable2 = (unsigned long *) &pca->pca_int[2].enable; in wildfire_init_irq_hw()
75 enable3 = (unsigned long *) &pca->pca_int[3].enable; in wildfire_init_irq_hw()
77 target0 = (unsigned long *) &pca->pca_int[0].target; in wildfire_init_irq_hw()
[all …]
/linux/drivers/clocksource/
H A Dtimer-ep93xx.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on a rewrite of arch/arm/mach-ep93xx/timer.c:
14 #include <linux/io-64-nonatomic-lo-hi.h>
26 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
27 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
28 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
29 * is free-running, and can't generate interrupts.
32 * most common values of HZ divide 508 kHz nicely. We pick the 32 bit
38 * a stable 40 bit time base.
45 #define EP93XX_TIMER123_CONTROL_ENABLE BIT(7)
[all …]
/linux/arch/mips/loongson64/
H A Ddma.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/dma-direct.h>
10 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in phys_to_dma()
11 * Loongson-3's 48bit address space and embed it into 40bit */ in phys_to_dma()
19 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in dma_to_phys()
20 * Loongson-3's 48bit address space and embed it into 40bit */ in dma_to_phys()
/linux/drivers/net/wireless/nxp/nxpwifi/
H A Dcfp.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2011-2024 NXP
47 /* LGI 40M */
51 /* SGI 40M */
82 /* LG 40M */
86 /* SG 40M */
115 /* LG 40M */
119 /* SG 40M */
173 /* 20M: bw=0, 40M: bw=1, 80M: bw=2, 160M: bw=3 */ in nxpwifi_index_to_acs_data_rate()
180 rate = ac_mcs_rate_nss2[2 * (3 - bw) + gi][mcs_index]; in nxpwifi_index_to_acs_data_rate()
[all …]
/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa3xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
19 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \
20 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \
21 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
23 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \
33 (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \
[all …]
/linux/drivers/hwmon/
H A Dltc4282.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
27 #define LTC4282_CTRL_OV_RETRY_MASK BIT(0)
28 #define LTC4282_CTRL_UV_RETRY_MASK BIT(1)
29 #define LTC4282_CTRL_OC_RETRY_MASK BIT(2)
30 #define LTC4282_CTRL_ON_ACTIVE_LOW_MASK BIT(5)
31 #define LTC4282_CTRL_ON_DELAY_MASK BIT(6)
37 #define LTC4282_OV_FAULT_MASK BIT(0)
38 #define LTC4282_UV_FAULT_MASK BIT(1)
41 #define LTC4282_OC_FAULT_MASK BIT(2)
[all …]
/linux/drivers/auxdisplay/
H A Dpanel.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2000-2008, Willy Tarreau <w@1wt.eu>
5 * Copyright (C) 2016-2017 Glider bvba
10 * The LCD module may either be an HD44780-like 8-bit parallel LCD, or a 1-bit
15 * data output pins or to the ground. The combinations have to be hard-coded
22 * - the initialization/deinitialization process is very dirty and should
26 * - document 24 keys keyboard (3 rows of 8 cols, 32 diodes + 2 inputs)
27 * - make the LCD a part of a virtual screen of Vx*Vy
28 * - make the inputs list smp-safe
29 * - change the keyboard to a double mapping : signals -> key_id -> values
[all …]
/linux/arch/x86/lib/
H A Dcsum-partial_64.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/x86_64/lib/csum-partial.c
6 * in an architecture-specific manner due to speed.
12 #include <asm/word-at-a-time.h>
35 * Returns a 32bit checksum.
41 * checksums on IPv6 headers (40 bytes) and other small parts.
42 * it's best to have buff aligned on a 64-bit boundary
48 /* Do two 40-byte chunks in parallel to get better ILP */ in csum_partial()
53 temp64_2 = update_csum_40b(temp64_2, buff + 40); in csum_partial()
55 len -= 80; in csum_partial()
[all …]
/linux/Documentation/arch/powerpc/
H A Dassociativity.rst9 are represented as being members of a sub-grouping domain. This performance
17 Hypervisor indicates the type/form of associativity used via "ibm,architecture-vec-5 property".
18 Bit 0 of byte 5 in the "ibm,architecture-vec-5" property indicates usage of Form 0 or Form 1.
20 bit 2 of byte 5 in the "ibm,architecture-vec-5" property is used.
23 ------
27 ------
28 With Form 1 a combination of ibm,associativity-reference-points, and ibm,associativity
34 The “ibm,associativity-reference-points” property contains a list of one or more numbers
43 if they belong to the same higher-level domains. For mismatch at every higher
48 -------
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/linux/arch/mips/include/asm/octeon/
H A Dcvmx.h7 * Copyright (c) 2003-2017 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
42 /* These macros for use when using 32 bit pointers. */
56 #include <asm/octeon/cvmx-asm.h>
57 #include <asm/octeon/cvmx-packet.h>
58 #include <asm/octeon/cvmx-sysinfo.h>
60 #include <asm/octeon/cvmx-ciu-defs.h>
61 #include <asm/octeon/cvmx-ciu3-defs.h>
62 #include <asm/octeon/cvmx-gpio-defs.h>
[all …]
/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_netdev.c1 // SPDX-License-Identifier: GPL-2.0+
12 /* The IFH bit position of the first VSTAX bit. This is because the
13 * VSTAX bit positions in Data sheet is starting from zero.
21 /* Max width is 5 bytes - 40 bits. In worst case this will
22 * spread over 6 bytes - 48 bits
24 compiletime_assert(width <= 40, \
35 u32 bit = (pos % 8); __ifh_encode_bitfield() local
[all...]
/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-nvm-parse.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2015, 2018-2026 Intel Corporation
4 * Copyright (C) 2016-2017 Intel Deutschland GmbH
10 #include "iwl-nvm-utils.h"
11 #include "mei/iwl-mei.h"
14 * enum iwl_nvm_sbands_flags - modification flags for the channel profiles
17 * @IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ: disallow 40, 80 and 160MHz on 5GHz
20 IWL_NVM_SBANDS_FLAGS_LAR = BIT(0),
21 IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ = BIT(1),
25 * enum iwl_puncturing_status - EHT puncturing status from MCC capabilities
[all …]
/linux/sound/soc/codecs/
H A Dmsm8916-wcd-digital.c1 // SPDX-License-Identifier: GPL-2.0
21 #define CLK_RX_RESET_B1_CTL_TX1_RESET_MASK BIT(0)
22 #define CLK_RX_RESET_B1_CTL_TX2_RESET_MASK BIT(1)
30 #define DMIC_B1_CTL_DMIC0_CLK_EN_MASK BIT(0)
31 #define DMIC_B1_CTL_DMIC0_CLK_EN_ENABLE BIT(0)
34 #define RX_I2S_CTL_RX_I2S_MODE_MASK BIT(5)
35 #define RX_I2S_CTL_RX_I2S_MODE_16 BIT(5)
45 #define TX_I2S_CTL_TX_I2S_MODE_MASK BIT(
[all...]
/linux/drivers/mtd/nand/spi/
H A Dgigadevice.c1 // SPDX-License-Identifier: GPL-2.0
27 /* Feature bit definitions */
28 #define GD_FEATURE_NR BIT(3) /* Normal Read(1=normal,0=continuous) */
29 #define GD_FEATURE_CRDC BIT(2) /* Continuous Read Dummy */
81 struct gigadevice_priv *priv = spinand->priv; in gd5fxgm9_get_eccsr()
88 ret = spi_mem_exec_op(spinand->spimem, &op); in gd5fxgm9_get_eccsr()
92 if (priv->continuous_read) in gd5fxgm9_get_eccsr()
111 ret = gd5fxgm9_get_eccsr(spinand, spinand->scratchbuf); in gd5fxgm9_ecc_get_status()
113 return nanddev_get_ecc_conf(nand)->strength; in gd5fxgm9_ecc_get_status()
115 eccsr = *spinand->scratchbuf; in gd5fxgm9_ecc_get_status()
[all …]
/linux/arch/powerpc/lib/
H A Dchecksum_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains assembly-language implementations
4 * of IP-style 1's complement checksum routines.
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
19 * and adds in "sum" (32-bit).
35 rldicl. r6,r3,64-1,64-2 /* r6 = (r3 >> 1) & 0x3 */
62 stdu r1,-STACKFRAMESIZE(r1)
83 ld r14,40(r3)
110 ld r14,40(r3)
176 rldicl r4,r0,32,0 /* fold two 32 bit halves together */
[all …]
/linux/Documentation/devicetree/bindings/ufs/
H A Dsnps,tc-dwc-g210.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/snps,tc-dwc-g210.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Wei <liwei213@huawei.com>
18 - snps,dwc-ufshcd-1.40a
20 - compatible
23 - $ref: ufs-common.yaml
28 - enum:
29 - snps,g210-tc-6.00-20bit
[all …]
/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include "clk-uniphier.h"
12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
25 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
[all …]
/linux/arch/m68k/fpsp040/
H A Dfpsp.h11 | fpsp.h --- stack frame offsets during FPSP exception handling
18 | link a6,#-LOCAL_SIZE
19 | fsave -(a7)
20 | movem.l d0-d1/a0-a1,USER_DA(a6)
21 | fmovem.x fp0-fp3,USER_FP0(a6)
26 | A7 ---> +-------------------------------+
30 | +-------------------------------+
36 | +-------------------------------+
37 | A6 ---> | Saved A6 |
38 | +-------------------------------+
[all …]
/linux/lib/
H A Dbitmap.c1 // SPDX-License-Identifier: GPL-2.0-only
32 * endian architectures. See the big-endian headers
33 * include/asm-ppc64/bitops.h and include/asm-s390/bitops.h
83 * __bitmap_shift_right - logical right shift of the bits in a bitmap
89 * Shifting right (dividing) means moving bits in the MS -> LS bit
110 if (off + k + 1 == lim - 1) in __bitmap_shift_right()
112 upper <<= (BITS_PER_LONG - rem); in __bitmap_shift_right()
115 if (off + k == lim - 1) in __bitmap_shift_right()
121 memset(&dst[lim - off], 0, off*sizeof(unsigned long)); in __bitmap_shift_right()
127 * __bitmap_shift_left - logical left shift of the bits in a bitmap
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_ethtool.h1 /* SPDX-License-Identifier: GPL-2.0-only */
66 * Array index corresponds to HW PHY type bit, see
101 [30] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full),
102 [31] = ICE_PHY_TYPE(40GB, 40000baseSR4_Full),
103 [32] = ICE_PHY_TYPE(40GB, 40000baseLR4_Full),
104 [33] = ICE_PHY_TYPE(40GB, 40000baseKR4_Full),
105 [34] = ICE_PHY_TYPE(40GB, 40000baseSR4_Full),
106 [35] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full),
111 [40] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
138 * Array index corresponds to HW PHY type bit, see
H A Dice_ptp_hw.c1 // SPDX-License-Identifier: GPL-2.0
24 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
26 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
28 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
29 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
34 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
39 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
41 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
43 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
44 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
[all …]
/linux/drivers/net/ppp/
H A Dppp_mppe.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 #define MPPE_MAX_KEY_LEN 16 /* largest key length (128-bit) */
6 #define MPPE_OPT_40 0x01 /* 40 bit */
7 #define MPPE_OPT_128 0x02 /* 128 bit */
10 #define MPPE_OPT_56 0x08 /* 56 bit */
19 * names above since C and H are the same bit. We could do a u_int32
25 #define MPPE_L_BIT 0x20 /* 40-bit */
26 #define MPPE_S_BIT 0x40 /* 128-bit */
27 #define MPPE_M_BIT 0x80 /* 56-bit, not supported */
30 /* Does not include H bit; used for least significant octet only. */
[all …]
/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_regs.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
3 /* This file is autogenerated by cml-utils 2021-10-10 13:25:08 +0200.
46 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ BIT(16)
61 #define ANA_ADVLEARN_VLAN_CHK BIT(0)
73 #define ANA_ANAINTR_INTR BIT(1)
79 #define ANA_ANAINTR_INTR_ENA BIT(0)
172 #define ANA_PGID_CFG_OBEY_VLAN BIT(0)
179 #define ANA_MACHDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 40, 0, 1, 4)
187 #define ANA_MACACCESS_CHANGE2SW BIT(17)
193 #define ANA_MACACCESS_MAC_CPU_COPY BIT(16)
[all …]
/linux/arch/m68k/include/asm/
H A Dmcfgpio.h1 /* SPDX-License-Identifier: GPL-2.0-only */
28 return -EINVAL; in __gpio_get_value()
39 return -EINVAL; in __gpio_to_irq()
47 return -EINVAL; in gpio_direction_input()
55 return -EINVAL; in gpio_direction_output()
63 return -EINVAL; in gpio_request()
77 * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
80 * input; some require a read-modify-write access to change an output, others
94 /* These parts have GPIO organized by 8 bit ports */
103 /* These parts have GPIO organized by 16 bit ports */
[all …]

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