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/linux/drivers/video/fbdev/kyro/
H A DSTG4000OverlayDevice.c26 #define STG4000_PRIM_ALIGN 4
35 #define STG4000_OVRL_NUM_PIX 4
57 /*clipped on-screen pixel position of overlay */
63 /*clipped pixel pos of source data within buffer thses need to be 128 bit word aligned */
69 /* on-screen pixel position of overlay */
111 CLEAR_BITS_FRM_TO(4, 7); in ResetOverlayRegisters()
152 return -EINVAL; in CreateOverlaySurface()
155 /* Stride in 16 byte words - 16Bpp */ in CreateOverlaySurface()
184 /* Only bits 24:4 of the Overlay address */ in CreateOverlaySurface()
185 tmp |= (ulOverlayOffset >> 4); in CreateOverlaySurface()
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/linux/include/video/
H A Dudlfb.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * DisplayLink X server as yet - need both to be modified in tandem
59 /* blit-only rendering path metrics, exposed through sysfs */
60 atomic_t bytes_rendered; /* raw pixel-bytes driver asked to render */
63 atomic_t cpu_kcycles_used; /* transpired during pixel processing */
71 /* -BULK_SIZE as per usb-skeleton. Can we get full page and avoid overhead? */
73 #define MAX_TRANSFER (PAGE_SIZE*16 - BULK_SIZE)
74 #define WRITES_IN_FLIGHT (4)
85 #define MIN_RLX_PIX_BYTES 4
96 #define DL_DEFIO_WRITE_DELAY msecs_to_jiffies(HZ <= 300 ? 4 : 10) /* optimal value for 720p vide…
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/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,padding.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
16 width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
24 - enum:
25 - mediatek,mt8188-disp-padding
26 - mediatek,mt8195-mdp3-padding
27 - items:
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/linux/drivers/media/platform/verisilicon/
H A Dhantro_hevc.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <media/v4l2-mem2mem.h>
14 #define VERT_FILTER_RAM_SIZE 8 /* bytes per pixel row */
17 * 128 bits per 4x4 tile = 128/(8*4) bytes per row
19 #define BSD_CTRL_RAM_SIZE 4 /* bytes per pixel row */
21 #define VERT_SAO_RAM_SIZE 48 /* bytes per pixel */
35 struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec; in hantro_hevc_ref_init()
37 hevc_dec->ref_bufs_used = 0; in hantro_hevc_ref_init()
43 struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec; in hantro_hevc_get_ref_buf()
48 if (hevc_dec->ref_bufs_poc[i] == poc) { in hantro_hevc_get_ref_buf()
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/linux/drivers/gpu/drm/meson/
H A Dmeson_osd_afbcd.c1 // SPDX-License-Identifier: GPL-2.0+
30 * - basic AFBC buffer for RGB32 only, thus YTR feature is mandatory
31 * - SPARSE layout and SPLIT layout
32 * - only 16x16 superblock
35 * decoded pixel stream to the OSD1 Plane pixel composer.
39 * to 4 surfaces, one for each of the 4 available OSDs.
43 * - basic AFBC buffer for multiple RGB and YUV pixel formats
44 * - SPARSE layout and SPLIT layout
45 * - 16x16 and 32x8 "wideblk" superblocks
46 * - Tiled header
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/linux/Documentation/admin-guide/media/
H A Dstarfive_camss.rst1 .. SPDX-License-Identifier: GPL-2.0
10 ------------
24 ----------------------------------
28 |\ +---------------+ +-----------+
29 +----------+ | \ | | | |
31 | MIPI |----->| |----->| ISP |----->| |
33 +----------+ | | | | | Memory |
34 |MUX| +---------------+ | Interface |
35 +----------+ | | | |
36 | | | |---------------------------->| |
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H A Dqcom_camss.rst1 .. SPDX-License-Identifier: GPL-2.0
9 ------------
25 ----------------------------------
30 - 2 / 3 CSIPHY modules. They handle the Physical layer of the CSI2 receivers.
32 - 2 / 4 CSID (CSI Decoder) modules. They handle the Protocol and Application
36 - ISPIF (ISP Interface) module. Handles the routing of the data streams from
38 - 1 / 2 VFE (Video Front End) module(s). Contain a pipeline of image processing
39 hardware blocks. The VFE has different input interfaces. The PIX (Pixel) input
48 -----------------------
52 - Input from camera sensor via CSIPHY;
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/linux/drivers/media/platform/samsung/s5p-jpeg/
H A Djpeg-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* linux/drivers/media/platform/samsung/s5p-jpeg/jpeg-core.h
15 #include <media/v4l2-device.h>
16 #include <media/v4l2-fh.h>
17 #include <media/v4l2-ctrls.h>
19 #define S5P_JPEG_M2M_NAME "s5p-jpeg"
21 #define JPEG_MAX_CLOCKS 4
45 #define SJPEG_FMT_FLAG_S5P (1 << 4)
53 #define S5P_JPEG_DISABLE -1
62 #define S5P_JPEG_MAX_MARKER 4
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/linux/drivers/gpu/ipu-v3/
H A Dipu-di.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
14 #include <video/imx-ipu-v3.h>
15 #include "ipu-prv.h"
23 struct clk *clk_di_pixel; /* resulting pixel clock */
49 DI_PIN15 = 4,
63 DI_SYNC_VSYNC = 4,
76 #define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1))
77 #define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1))
78 #define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2))
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/linux/drivers/media/platform/ti/omap3isp/
H A Dispresizer.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - Resizer module
42 * "TRM ES3.1, table 12-46"
59 * 7-tap mode is for scale factors 0.25x to 0.5x.
60 * 4-tap mode is for scale factors 0.5x to 4.0x.
64 /* For 8-phase 4-tap horizontal filter: */
75 /* For 8-phase 4-tap vertical filter: */
86 /* For 4-phase 7-tap horizontal filter: */
94 /* For 4-phase 7-tap vertical filter: */
102 * The dummy padding is required in 7-tap mode because of how the
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/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_buffer.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2018 Etnaviv Project
27 u32 *vaddr = (u32 *)buffer->vaddr; in OUT()
29 BUG_ON(buffer->user_size >= buffer->size); in OUT()
31 vaddr[buffer->user_size / 4] = data; in OUT()
32 buffer->user_size += 4; in OUT()
40 buffer->user_size = ALIGN(buffer->user_size, 8); in CMD_LOAD_STATE()
51 buffer->user_size = ALIGN(buffer->user_size, 8); in CMD_END()
59 buffer->user_size = ALIGN(buffer->user_size, 8); in CMD_WAIT()
67 buffer->user_size = ALIGN(buffer->user_size, 8); in CMD_LINK()
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/linux/Documentation/userspace-api/media/v4l/
H A Dcrop.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
6 Image Cropping, Insertion and Scaling -- the CROP API
12 <selection-api>`. The new API should be preferred in most cases,
13 with the exception of pixel aspect ratio detection, which is
15 equivalent in the SELECTION API. See :ref:`selection-vs-crop` for a
62 .. _crop-scale:
64 .. kernel-figure:: crop.svg
66 :align: center
81 :ref:`vbi-hsync`). Vertically ITU-R line numbers of the first field
82 (see ITU R-525 line numbering for :ref:`525 lines <vbi-525>` and for
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/linux/drivers/video/fbdev/
H A Ds3c-fb.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/video/s3c-fb.c
5 * Copyright 2008-2010 Simtec Electronics
15 #include <linux/dma-mapping.h>
31 * setting of the alpha-blending functions that each window has, so only
35 * output timings and as the control for the output power-down state.
38 /* note, the previous use of <mach/regs-fb.h> to get platform specific data
58 #define VALID_BPP(x) (1 << ((x) - 1))
67 * struct s3c_fb_variant - fb variant information
116 * @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel.
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H A Dtgafb.c2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
37 #define TGA_BUS_TC(dev) (dev->bus == &tc_bus_type)
118 return tgafb_register(&pdev->dev); in tgafb_pci_register()
123 tgafb_unregister(&pdev->dev); in tgafb_pci_unregister()
135 { "DEC ", "PMAGD-AA" },
169 * tgafb_check_var - Optional function. Validates a var passed in.
176 struct tga_par *par = (struct tga_par *)info->par; in tgafb_check_var()
178 if (!var->pixclock) in tgafb_check_var()
179 return -EINVAL; in tgafb_check_var()
181 if (par->tga_type == TGA_TYPE_8PLANE) { in tgafb_check_var()
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H A Dpxafb.c5 * Copyright (C) 2004 Jean-Frederic Clere.
21 * linux-arm-kernel@lists.arm.linux.org.uk
31 * Copyright (C) 2006-2008 Marvell International Ltd.
50 #include <linux/dma-mapping.h>
68 #include <linux/platform_data/video-pxafb.h>
76 #include "pxa3xx-regs.h"
99 return __raw_readl(fbi->mmio_base + off); in lcd_readl()
105 __raw_writel(val, fbi->mmio_base + off); in lcd_writel()
123 if (fbi->task_state == C_ENABLE && state == C_REENABLE) in pxafb_schedule_work()
124 state = (u_int) -1; in pxafb_schedule_work()
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/linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/
H A Ddcn32_mmhubbub.c34 mcif_wb30->mcif_wb_regs->reg
37 mcif_wb30->base.ctx
41 mcif_wb30->mcif_wb_shift->field_name, mcif_wb30->mcif_wb_mask->field_name
48 * unsigned long long luma_address[4]; //4 frame buffer
49 * unsigned long long chroma_address[4];
52 * unsigned int warmup_pitch=0x10; //256B align, the page size is 4KB when it is 0x10
54 * unsigned int time_per_pixel; // time per pixel, in ns
58 * unsigned int cli_watermark[4]; //4 group urgent watermark
59 * unsigned int pstate_watermark[4]; //4 group pstate watermark
72 * 4. wbif_dump_status(), option, for debug purpose
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/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mmhubbub.c34 mcif_wb30->mcif_wb_regs->reg
37 mcif_wb30->base.ctx
41 mcif_wb30->mcif_wb_shift->field_name, mcif_wb30->mcif_wb_mask->field_name
48 * unsigned long long luma_address[4]; //4 frame buffer
49 * unsigned long long chroma_address[4];
52 * unsigned int warmup_pitch=0x10; //256B align, the page size is 4KB when it is 0x10
54 * unsigned int time_per_pixel; // time per pixel, in ns
58 * unsigned int cli_watermark[4]; //4 group urgent watermark
59 * unsigned int pstate_watermark[4]; //4 group pstate watermark
72 * 4. wbif_dump_status(), option, for debug purpose
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/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_fwif_client.h1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
27 * Minimum PB = Base Pages + (NUM_TE_PIPES-1)*16K + (NUM_VCE_PIPES-1)*64K +
39 * Since the max of NUM_TE_PIPES and NUM_VCE_PIPES is 4, we have a hard limit
40 * of 4GB minus the Minimum PB. For convenience we take the smaller power-of-2
66 /* Disable pixel merging for this render. */
209 /* All values below the ALIGN(8) must be 64 bit. */
252 /* Stride IN BYTES for Z-Buffer in case of RTAs. */
254 /* Stride IN BYTES for S-Buffer in case of RTAs. */
320 * single RGXFW_ALIGN to align all the 64 bit values in the second section.
/linux/drivers/gpu/drm/rockchip/
H A Drockchip_drm_vop2.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Author: Andy Yan <andy.yan@rock-chips.com>
12 #include <linux/media-bus-format.h>
44 +----------+ +-------------+ +-----------+
47 +----------+ +-------------+ +---------------+ +-------------+ +-----------+
48 +----------+ +-------------+ |N from 6 layers| | |
49 | Cluster | | Sel 1 from 6| | Overlay0 +--->| Video Port0 | +-----------+
51 +----------+ +-------------+ +---------------+ +-------------+ | LVDS |
52 +----------+ +-------------+ +-----------+
54 | window0 | | Layer2 | +---------------+ +-------------+ +-----------+
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_fb.c1 // SPDX-License-Identifier: MIT
6 #include <linux/dma-fence.h>
7 #include <linux/dma-resv.h>
26 #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a))
31 * the cache-line pairs. The compression state of the cache-line pair
32 * is specified by 2 bits in the CCS. Each CCS cache-line represents
33 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
34 * cache-line-pairs. CCS is always Y tiled."
38 * lines on the main surface. Since each pixel is 4 bytes, this gives
44 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
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/linux/drivers/staging/media/tegra-video/
H A Dtegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
32 #define VI_CSI_PP_FRAME_START(port) (5 + (port) * 4)
33 #define VI_CSI_MW_ACK_DONE(port) (7 + (port) * 4)
64 /* Tegra210 CSI Pixel Parser registers: Starts from 0x838, offset 0x0 */
68 #define CSI_PP_PACKET_HEADER_SENT BIT(4)
79 #define CSI_PP_TOP_FIELD_FRAME_MASK_OFFSET 4
150 writel_relaxed(val, chan->vi->iomem + addr); in tegra_vi_write()
155 return readl_relaxed(chan->vi->iomem + addr); in tegra_vi_read()
164 vi_csi_base = chan->vi->iomem + TEGRA210_VI_CSI_BASE(portno); in vi_csi_write()
174 vi_csi_base = chan->vi->iomem + TEGRA210_VI_CSI_BASE(portno); in vi_csi_read()
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/linux/drivers/media/platform/st/sti/hva/
H A Dhva-h264.c1 // SPDX-License-Identifier: GPL-2.0
9 #include "hva-hw.h"
26 #define SEARCH_WINDOW_BUFFER_MAX_SIZE(w) ((4 * MB_W(w) + 42) * 256 * 3 / 2)
29 #define SLICE_HEADER_SIZE (4 * 16)
32 /* source buffer copy in YUV 420 MB-tiled format with size=16*256*3/2 */
36 * 4 lines of pixels (in Luma, Chroma blue and Chroma red) of top MB
37 * for deblocking with size=4*16*MBx*2
39 #define LOCAL_RECONSTRUCTED_BUFFER_MAX_SIZE(w) (4 * 16 * MB_W(w) * 2)
69 {V4L2_MPEG_VIDEO_H264_LEVEL_3_1, 108000, 3600, 14000, 14000, 4},
70 {V4L2_MPEG_VIDEO_H264_LEVEL_3_2, 216000, 5120, 20000, 20000, 4},
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/linux/drivers/gpu/drm/omapdrm/
H A Domap_dmm_tiler.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
12 #include <linux/dma-mapping.h>
50 .slot_w = 1 << (SLOT_WIDTH_BITS - (xshift)), \
51 .slot_h = 1 << (SLOT_HEIGHT_BITS - (yshift)), \
55 u32 x_shft; /* unused X-bits (as part of bpp) */
56 u32 y_shft; /* unused Y-bits (as part of bpp) */
57 u32 cpp; /* bytes/chars per pixel */
63 [TILFMT_32BIT] = GEOM(1, 1, 4),
68 /* lookup table for registers w/ per-engine instances */
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/linux/drivers/gpu/drm/bridge/
H A Dtc358767.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
27 #include <linux/media-bus-format.h>
44 /* DSI D-PHY Layer registers */
77 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
110 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
128 #define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */
129 #define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */
155 #define ENBDSIRX (1 << 4)
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/linux/drivers/gpu/drm/imx/ipuv3/
H A Dimx-ldb.c1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX drm driver - LVDS display bridge
11 #include <linux/media-bus-format.h>
13 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
33 #include "imx-drm.h"
35 #define DRIVER_NAME "imx-ldb"
43 #define LDB_SPLIT_MODE_EN (1 << 4)
73 return container_of(e, struct imx_ldb_encoder, encoder)->channel; in enc_to_imx_ldb_ch()
87 struct clk *clk_sel[4]; /* parent of display clock */
88 struct clk *clk_parent[4]; /* original parent of clk_sel */
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