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/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15-tc1.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15 MPCore (V2P-CA15)
8 * HBI-0237A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15";
18 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
[all …]
/linux/drivers/phy/broadcom/
H A Dphy-bcm-sr-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
40 * struct sr_pcie_phy - Stingray PCIe PHY
53 * struct sr_pcie_phy_core - Stingray PCIe PHY core control
83 /* PIPEMUX = 2, EP 4x4 */
85 /* PIPEMUX = 3, RC 2x8, cores 0, 7 */
87 /* PIPEMUX = 4, RC 4x4, cores 0, 1, 6, 7 */
89 /* PIPEMUX = 5, RC 8x2, all 8 cores */
91 /* PIPEMUX = 6, RC 3x4 + 2x2, cores 0, 2, 3, 6, 7 */
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/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A Duncore-power.json88 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
97 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
106 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
115 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
124 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
133 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
142 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
151 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
160 …can use all four counters with this event, so it is possible to track up to 4 configurable bands. …
169 …can use all four counters with this event, so it is possible to track up to 4 configurable bands. …
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/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Duncore-power.json92 "BriefDescription": "Core 4 C State Transition Cycles",
146 "BriefDescription": "Deep C State Rejection - Core 0",
155 "BriefDescription": "Deep C State Rejection - Core 1",
164 "BriefDescription": "Deep C State Rejection - Core 10",
173 "BriefDescription": "Deep C State Rejection - Core 11",
182 "BriefDescription": "Deep C State Rejection - Core 12",
191 "BriefDescription": "Deep C State Rejection - Core 13",
200 "BriefDescription": "Deep C State Rejection - Core 14",
209 "BriefDescription": "Deep C State Rejection - Core 2",
218 "BriefDescription": "Deep C State Rejection - Core 3",
[all …]
/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Duncore-power.json178 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
187 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
196 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
205 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
214 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
223 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
232 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
241 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
250 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
259 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
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/linux/tools/power/cpupower/man/
H A Dcpupower-set.11 .TH CPUPOWER\-SET "1" "22/02/2011" "" "cpupower Manual"
3 cpupower\-set \- Set processor power related kernel or hardware configurations
6 .B cpupower set [ \-b VAL | \-e POLICY | \-m MODE | \-t BOOL ]
13 Some options are platform wide, some affect single cores. By default values
14 are applied on all cores. How to modify single core configurations is
15 described in the cpupower(1) manpage in the \-\-cpu option section. Whether an
16 option affects the whole system or can be applied to individual cores is
24 \-\-perf-bias, \-b
25 .RS 4
30 The range of valid numbers is 0-15, where 0 is maximum
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H A Dcpupower.13 cpupower \- Shows and sets processor power related values
6 .B cpupower [ \-c cpulist ] <command> [ARGS]
8 .B cpupower \-v|\-\-version
10 .B cpupower \-h|\-\-help
16 The manpages of the commands (cpupower\-<command>(1)) provide detailed
22 \-\-help, \-h
23 .RS 4
27 \-\-cpu cpulist, \-c cpulist
28 .RS 4
29 Only show or set values for specific cores.
[all …]
H A Dcpupower-monitor.11 .TH CPUPOWER\-MONITOR "1" "22/02/2011" "" "cpupower Manual"
3 cpupower\-monitor \- Report processor frequency and idle statistics
7 .RB "\-l"
10 .RB [ -c ] [ "\-m <mon1>," [ "<mon2>,..." ] ]
11 .RB [ "\-i seconds" ]
14 .RB [ -c ][ "\-m <mon1>," [ "<mon2>,..." ] ]
18 \fBcpupower-monitor \fP reports processor topology, frequency and idle power
22 \fBcpupower-monitor \fP implements independent processor sleep state and
24 directly reading out hardware registers. Use \-l to get an overview which are
29 \-l
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H A Dcpupower-idle-set.11 .TH "CPUPOWER-IDLE-SET" "1" "0.1" "" "cpupower Manual"
4 cpupower\-idle\-set \- Utility to set cpu idle state specific kernel options
7 cpupower [ \-c cpulist ] idle\-set [\fIoptions\fP]
10 The cpupower idle\-set subcommand allows to set cpu idle, also called cpu
16 \fB\-d\fR \fB\-\-disable\fR <STATE_NO>
19 \fB\-e\fR \fB\-\-enable\fR <STATE_NO>
22 \fB\-D\fR \fB\-\-disable-by-latency\fR <LATENCY>
27 \fB\-E\fR \fB\-\-enable-all\fR
34 .RS 4
52 .RS 4
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/linux/arch/arc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
90 source "arch/arc/plat-tb10x/Kconfig"
91 source "arch/arc/plat-axs10x/Kconfig"
92 source "arch/arc/plat-hsdk/Kconfig"
104 The original ARC ISA of ARC600/700 cores
110 ISA for the Next Generation ARC-HS cores
128 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
130 -Caches: New Prog Model, Region Flush
131 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
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/linux/drivers/net/can/esd/
H A Desd_402_pci-core.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2015 - 2016 Thomas Körper, esd electronic system design gmbh
3 * Copyright (C) 2017 - 2023 Stefan Mätje, esd electronics gmbh
10 #include <linux/dma-mapping.h>
50 struct acc_core *cores; member
59 /* Used if the esdACC FPGA is built as CAN-Classic version. */
66 .sjw_max = 4,
72 /* Used if the esdACC FPGA is built as CAN-FD version. */
103 irq_status = acc_card_interrupt(&card->ov, card->cores); in pci402_interrupt()
118 /* The FPGA hard IP PCIe core implements a 64-bit MSI Capability in pci402_set_msiconfig()
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/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Duncore-cache.json135 "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
141 …"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD…
256 "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
262 …"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 A…
377 "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
383 …"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL…
498 "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
504 …"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 B…
619 "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
625 …"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD…
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dbrcm,bus-axi.txt5 - compatible : brcm,bus-axi
7 - reg : iomem address range of chipcommon core
9 The cores on the AXI bus are automatically detected by bcma with the
12 BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
13 them manually through device tree. Use an interrupt-map to specify the
17 The top-level axi bus may contain children representing attached cores
19 detected (e.g. IRQ numbers). Also some of the cores may be responsible
25 compatible = "brcm,bus-axi";
28 #address-cells = <1>;
29 #size-cells = <1>;
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/linux/Documentation/admin-guide/device-mapper/
H A Dunstriped.rst2 Device-mapper "unstriped" target
8 The device-mapper "unstriped" target provides a transparent mechanism to
9 unstripe a device-mapper "striped" target to access the underlying disks
10 without having to touch the true backing block-device. It can also be
11 used to unstripe a hardware RAID-0 to access backing disks.
33 An example of undoing an existing dm-stripe
34 -------------------------------------------
36 This small bash script will setup 4 loop devices and use the existing
37 striped target to combine the 4 devices into one. It then will use
46 NUM=4
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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,pru-consumer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,pru-consumer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
25 $ref: /schemas/types.yaml#/definitions/phandle-array
32 firmware-name:
33 $ref: /schemas/types.yaml#/definitions/string-array
37 firmwares for the PRU cores, the default firmware for the core from
39 correspond to the PRU cores listed in the 'ti,prus' property
[all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-cache.json47 "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4",
53 …"PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD…
168 "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4",
174 …"PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 A…
289 "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4",
295 …"PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL…
410 "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4",
416 …"PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 B…
531 "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4",
537 …"PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD…
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/linux/Documentation/admin-guide/pm/
H A Dintel-speed-select.rst1 .. SPDX-License-Identifier: GPL-2.0
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
47 # intel-speed-select --help
49 The top-level help describes arguments and features. Notice that there is a
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/linux/arch/s390/kernel/
H A Dhiperdispatch.c1 // SPDX-License-Identifier: GPL-2.0
11 * Dynamically calculates the optimum number of high capacity COREs
14 * During topology updates the CPU capacities are always re-adjusted.
18 * -> hiperdispatch's reoccuring work function reads CPU capacities to
20 * -> during a topology update hiperdispatch's adjustment function
37 * - single CORE, with N threads, running N tasks
38 * - N separate COREs running N tasks,
39 * using individual COREs for individual tasks yield better
43 * Hiperdispatch tries to hint scheduler to use individual COREs for
44 * each task, as long as steal time on those COREs are less than 30%,
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/linux/Documentation/arch/x86/
H A Damd-hfi.rst1 .. SPDX-License-Identifier: GPL-2.0
13 --------
16 architectural class and CPUs are comprised of cores of various efficiency and
17 power capabilities: performance-oriented *classic cores* and power-efficient
18 *dense cores*. As such, power management strategies must be designed to
26 sending background threads to the dense cores while sending high priority
27 threads to the classic cores. From a performance perspective, sending
28 background threads to dense cores can free up power headroom and allow the
29 classic cores to optimally service demanding threads. Furthermore, the area
30 optimized nature of the dense cores allows for an increasing number of
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/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_defs.h1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
84 * the number of clusters by 4 and round up
86 #define ROGUE_REQ_NUM_PHANTOMS(CLUSTERS) (((CLUSTERS) + 3U) / 4U)
87 #define ROGUE_REQ_NUM_BERNADOS(CLUSTERS) (((CLUSTERS) + 3U) / 4U)
88 #define ROGUE_REQ_NUM_BLACKPEARLS(CLUSTERS) (((CLUSTERS) + 3U) / 4U)
101 (n) * (ROGUE_CR_BIF_CAT_BASE1 - ROGUE_CR_BIF_CAT_BASE0))
105 (n) * (ROGUE_CR_FWCORE_MEM_CAT_BASE1 - \
120 #define ROGUE_CSRM_LINE_SIZE_IN_DWORDS (64 * 4 * 4)
127 * (in dwords/32-bit registers).
143 /* for nohw multicore return max cores possible to client */
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H A Dpvr_rogue_cr_defs_client.h1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
7 /* clang-format off */
10 * This register controls the anti-aliasing mode of the Tiling Co-Processor, independent control is
15 * 2xmsaa is achieved by enabling Y - TE does AA on Y plane only
16 * 4xmsaa is achieved by enabling Y and X - TE does AA on X and Y plane
17 * 8xmsaa not supported by XE cores
20 * 2xmsaa is achieved by enabling X2 - does not affect TE
21 * 4xmsaa is achieved by enabling Y and X2 - TE does AA on Y plane only
22 * 8xmsaa is achieved by enabling Y, X and X2 - TE does AA on X and Y plane
23 * 8xmsaa not supported by XE cores
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/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
32 DesignWare(R) Cores Ethernet MAC 10/100/1000 Universal version 3.70a
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
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/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A Dcache.json113 …on": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the…
386 "BriefDescription": "Core-originated cacheable demand requests missed LLC.",
394 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.",
402 …d load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise E…
407 …-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (sa…
412 …Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS).",
417 …-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (sa…
422 …d uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise …
431 …ed load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS).",
440 … uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS).",
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/linux/arch/arm64/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
287 ARM 64-bit (AArch64) Linux support.
295 # required due to use of the -Zfixed-x18 flag.
298 # -Zsanitizer=shadow-call-stack flag.
308 depends on $(cc-option,-fpatchable-function-entry=2)
320 default 4
326 default 4
334 # VA_BITS - PTDESC_TABLE_SHIFT
401 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
402 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
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/linux/arch/arm/include/asm/
H A Dcputype.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define CPUID_MPUIR 4
35 #define CPUID_EXT_MMFR0 "c1, 4"
43 #define CPUID_EXT_ISAR4 "c2, 4"
46 #define CPUID_EXT_PFR2 "c3, 4"
59 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
93 /* DEC implemented cores */
96 /* Intel implemented cores */
99 #define ARM_CPU_REV_SA1110_B0 4
109 /* Qualcomm implemented cores */
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