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/freebsd/lib/libpmc/pmu-events/arch/x86/sandybridge/
H A Dcache.json5 "CounterHTOff": "0,1,2,3,4,5,6,7",
14 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 "CounterHTOff": "0,1,2,3,4,5,6,7",
32 "CounterHTOff": "0,1,2,3,4,5,6,7",
42 "CounterHTOff": "0,1,2,3,4,5,6,7",
52 "CounterHTOff": "0,1,2,3,4,5,6,7",
92 "CounterHTOff": "0,1,2,3,4,5,6,7",
101 "CounterHTOff": "0,1,2,3,4,5,6,7",
110 "CounterHTOff": "0,1,2,3,4,5,6,7",
119 "CounterHTOff": "0,1,2,3,4,5,6,7",
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/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca15-tc1.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15 MPCore (V2P-CA15)
8 * HBI-0237A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15";
18 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A Duncore-other.json11 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
23 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
166 "ScaleUnit": "4Bytes",
182 "ScaleUnit": "4Bytes",
198 "ScaleUnit": "4Bytes",
214 "ScaleUnit": "4Bytes",
227 "ScaleUnit": "4Bytes",
240 "ScaleUnit": "4Bytes",
253 "ScaleUnit": "4Bytes",
266 "ScaleUnit": "4Bytes",
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/freebsd/sys/dev/bhnd/bhndb/
H A Dbhndb_pci.c1 /*-
2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
36 * PCI-specific implementation for the BHNDB bridge driver.
38 * Provides support for bridging from a PCI parent bus to a BHND-compatible
39 * bus (e.g. bcma or siba) via a Broadcom PCI core configured in end-point
42 * This driver handles all initial generic host-level PCI interactions with a
43 * PCI/PCIe bridge core operating in endpoint mode. Once the bridged bhnd(4)
44 * bus has been enumerated, this driver works in tandem with a core-specific
67 #include <dev/bhnd/cores/pci/bhnd_pcireg.h>
112 struct bhnd_core_info **cores, u_int *ncores);
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H A Dbhndb.c1 /*-
2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
39 * a BHND-compatible bus (e.g. bcma or siba).
58 #include <dev/bhnd/cores/chipc/chipcreg.h>
80 struct bhnd_core_info *cores, u_int ncores,
86 struct bhnd_core_info *cores, u_int ncores,
90 struct bhnd_core_info *cores, u_int ncores,
119 * Default bhndb(4) implementation of DEVICE_PROBE().
122 * and is compatible with bhndb(4) bridges attached via bhndb_attach_bridge().
172 (unsigned long long) sc->chipid.enum_addr); in bhndb_child_location()
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H A Dbhndb_hwdata.c1 /*-
39 * Resource priority specifications shared by all bhndb(4) bridge
55 * Define a core priority record for all cores matching @p devclass
97 * bcma(4)-based PCI devices.
103 * Runtime access to these cores is not required, and no register
114 * These devices do not sit in a performance-critical path and can be
136 * All other cores are assumed to require efficient runtime access to
152 * siba(4)-based PCI devices.
158 * Runtime access to these cores is not required, and no register
169 * These devices do not sit in a performance-critical path and can be
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/freebsd/lib/libpmc/pmu-events/arch/x86/haswell/
H A Dcache.json5 "CounterHTOff": "0,1,2,3,4,5,6,7",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
56 "CounterHTOff": "0,1,2,3,4,5,6,7",
65 "CounterHTOff": "0,1,2,3,4,5,6,7",
75 "CounterHTOff": "0,1,2,3,4,5,6,7",
85 "CounterHTOff": "0,1,2,3,4,5,6,7",
95 "CounterHTOff": "0,1,2,3,4,5,6,7",
105 "CounterHTOff": "0,1,2,3,4,5,6,7",
115 "CounterHTOff": "0,1,2,3,4,5,6,7",
125 "CounterHTOff": "0,1,2,3,4,5,6,7",
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/freebsd/lib/libpmc/pmu-events/arch/x86/haswellx/
H A Dcache.json5 "CounterHTOff": "0,1,2,3,4,5,6,7",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
56 "CounterHTOff": "0,1,2,3,4,5,6,7",
65 "CounterHTOff": "0,1,2,3,4,5,6,7",
75 "CounterHTOff": "0,1,2,3,4,5,6,7",
85 "CounterHTOff": "0,1,2,3,4,5,6,7",
95 "CounterHTOff": "0,1,2,3,4,5,6,7",
105 "CounterHTOff": "0,1,2,3,4,5,6,7",
115 "CounterHTOff": "0,1,2,3,4,5,6,7",
125 "CounterHTOff": "0,1,2,3,4,5,6,7",
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/freebsd/lib/libpmc/pmu-events/arch/x86/skylakex/
H A Dcache.json5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
28 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
35 "CounterHTOff": "0,1,2,3,4,5,6,7",
47 "CounterHTOff": "0,1,2,3,4,5,6,7",
57 "CounterHTOff": "0,1,2,3,4,5,6,7",
67 "CounterHTOff": "0,1,2,3,4,5,6,7",
75 …n triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event.",
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Darm,vexpress-juno.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-jun
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/freebsd/share/man/man4/
H A Dsiba.434 .Bd -ragged -offset indent
41 .Bd -literal -offset indent
48 .Xr bhnd 4
55 These functional blocks, known as cores, use the Open Core Protocol
62 Not all cores contain both an initiator and a target agent.
63 Initiator agents are present in cores that contain
65 or DMA processors associated with communications cores.
67 .Xr bcma 4 ,
68 .Xr bhnd 4 ,
69 .Xr intro 4
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H A Dsmp.424 .Dd January 4, 2019
29 .Nd description of the FreeBSD Symmetric Multi-Processor kernel
35 kernel implements symmetric multi-processor support.
43 the read-only sysctl variable
46 The number of online threads per CPU core is available in the read-only sysctl
49 The number of physical CPU cores detected by the system is available in the
50 read-only sysctl variable
51 .Va kern.smp.cores .
54 allows specific CPUs on a multi-processor system to be disabled.
68 .Xr sched_ule 4
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/freebsd/lib/libpmc/pmu-events/arch/x86/jaketown/
H A Dcache.json5 "CounterHTOff": "0,1,2,3,4,5,6,7",
14 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 "CounterHTOff": "0,1,2,3,4,5,6,7",
32 "CounterHTOff": "0,1,2,3,4,5,6,7",
42 "CounterHTOff": "0,1,2,3,4,5,6,7",
52 "CounterHTOff": "0,1,2,3,4,5,6,7",
92 "CounterHTOff": "0,1,2,3,4,5,6,7",
101 "CounterHTOff": "0,1,2,3,4,5,6,7",
110 "CounterHTOff": "0,1,2,3,4,5,6,7",
119 "CounterHTOff": "0,1,2,3,4,5,6,7",
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/freebsd/sys/dev/bwn/
H A Dif_bwn_pcivar.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2016 Landon Fuller <landonf@FreeBSD.org>
35 /** bwn_pci per-instance state. */
54 * Early dual-band devices did not support accessing multiple PHYs
56 * WLAN cores.
58 * However, not all cards with two WLAN cores are fully populated;
65 * Some early devices shipped with unconnected ethernet cores; set
66 * this quirk to treat these cores as unpopulated.
71 * Some PCI/PCIe "Intensi-fi" chipsets shipped with floating USB
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/freebsd/usr.sbin/bhyve/
H A Dbhyverun.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
126 * The acceptance of a null specification ('-c ""') is by design to match the
136 set_config_value("cores", "1"); in bhyve_topology_parse()
144 errx(4, "Failed to allocate memory"); in bhyve_topology_parse()
151 else if (strncmp(cp, "cores=", strlen("cores=")) == 0) in bhyve_topology_parse()
152 set_config_value("cores", cp + strlen("cores=")); in bhyve_topology_parse()
165 return (-1); in bhyve_topology_parse()
178 errx(4, "Invalid value for %s: '%s'", key, value); in parse_int_value()
183 * Set the sockets, cores, threads, and guest_cpus variables based on
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/freebsd/lib/libomp/
H A Dkmp_i18n_default.inc2 // The file was generated from en_US.txt by message-converter.py on Sat Jul 27 14:17:03 2024. //
27 "value is not a multiple of 4k",
65 "cpuid leaf 4 not supported",
77 "cores",
111 "%1$s pragma (at %2$s:%3$s():%4$s)",
142 "Real-time scheduling policy is not supported.",
143 "OMP application is running at maximum priority with real-time scheduling policy. ",
187 "%1$s: range error ((%2$d-%3$d)/%4$d too big), not using affinity.",
207 …"Too many threads to use analytical guided scheduling - switching to iterative guided scheduling.",
240 "Error initializing affinity - not using affinity.",
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/freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/
H A Dcache.json5 "CounterHTOff": "0,1,2,3,4,5,6,7",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
58 "CounterHTOff": "0,1,2,3,4,5,6,7",
67 "CounterHTOff": "0,1,2,3,4,5,6,7",
77 "CounterHTOff": "0,1,2,3,4,5,6,7",
85 …on": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the…
87 "CounterHTOff": "0,1,2,3,4,5,6,7",
97 "CounterHTOff": "0,1,2,3,4,5,6,7",
107 "CounterHTOff": "0,1,2,3,4,5,6,7",
117 "CounterHTOff": "0,1,2,3,4,5,6,7",
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/freebsd/sys/amd64/vmm/
H A Dx86.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
64 * Compute ceil(log2(x)). Returns -1 if x is zero.
70 return (x == 0 ? -1 : order_base_2(x)); in log2()
83 unsigned int func, regs[4], logical_cpus, param; in x86_emulate_cpuid()
85 uint16_t cores, maxcpus, sockets, threads; in x86_emulate_cpuid() local
113 * no multi-core or SMT. in x86_emulate_cpuid()
140 vm_get_topology(vm, &sockets, &cores, &threads, in x86_emulate_cpuid()
152 width = MIN(0xF, log2(threads * cores)); in x86_emulate_cpuid()
153 logical_cpus = MIN(0xFF, threads * cores - 1); in x86_emulate_cpuid()
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/freebsd/lib/libpmc/pmu-events/arch/x86/sapphirerapids/
H A Duncore-other.json24 "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
64 "BriefDescription": "Write request of 4 bytes made by IIO Part0 to Memory",
77 "BriefDescription": "Write request of 4 bytes made by IIO Part1 to Memory",
90 "BriefDescription": "Write request of 4 bytes made by IIO Part2 to Memory",
103 "BriefDescription": "Write request of 4 bytes made by IIO Part3 to Memory",
116 … "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
129 … "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
142 … "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
155 … "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
579 …"BriefDescription": "TOR Inserts for DRds issued by iA Cores targeting PMM Mem that Missed the LLC…
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/freebsd/sys/dev/bhnd/
H A Dbhnd_erom_if.m1 #-
2 # Copyright (c) 2016-2017 Landon Fuller <landon@landonf.org>
43 # bhnd(4) device enumeration.
46 # tables used by bhnd(4) buses.
94 * @retval non-zero if an error occurs initializing the EROM parser,
114 * Parse all cores descriptors, returning the array in @p cores and the count
121 * @param[out] cores The table of parsed core descriptors.
122 * @param[out] num_cores The number of core records in @p cores.
125 * @retval non-zero if an error occurs, a regular unix error code will
130 struct bhnd_core_info **cores;
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/freebsd/lib/libpmc/pmu-events/arch/x86/broadwellx/
H A Dcache.json5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
28 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
57 "CounterHTOff": "0,1,2,3,4,5,6,7",
67 "CounterHTOff": "0,1,2,3,4,5,6,7",
77 "CounterHTOff": "0,1,2,3,4,5,6,7",
87 "CounterHTOff": "0,1,2,3,4,5,6,7",
97 "CounterHTOff": "0,1,2,3,4,5,6,7",
107 "CounterHTOff": "0,1,2,3,4,5,6,7",
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/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dbrcm,bus-axi.txt5 - compatible : brcm,bus-axi
7 - reg : iomem address range of chipcommon core
9 The cores on the AXI bus are automatically detected by bcma with the
12 BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
13 them manually through device tree. Use an interrupt-map to specify the
17 The top-level axi bus may contain children representing attached cores
19 detected (e.g. IRQ numbers). Also some of the cores may be responsible
25 compatible = "brcm,bus-axi";
28 #address-cells = <1>;
29 #size-cells = <1>;
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/freebsd/contrib/llvm-project/openmp/runtime/src/i18n/
H A Den_US.txt4 #//===----------
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/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dti,pru-consumer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,pru-consume
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/freebsd/share/man/man9/
H A Dbhnd.91 .\" Copyright (c) 2015-2016 Landon Fuller <landonf@FreeBSD.org>
354 .Fa "const struct bhnd_core_info *cores" "u_int num_cores"
392 .Bd -literal
398 .Bd -literal
406 .Bd -literal
414 .Bd -literal
417 .Bd -literal
427 .Bd -literal
435 .Bd -literal
442 .Bd -literal
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