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Searched +full:3 +full:cg +full:- +full:2019 (Results 1 – 6 of 6) sorted by relevance

/linux/sound/soc/sof/intel/
H A Dhda-ipc.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
6 * Copyright(c) 2019 Intel Corporation
16 * - DIPCTDR (HIPCIDR) in sideband IPC (cAVS 1.8+)
17 * - DIPCT in cAVS 1.5 IPC
20 * - DIPCTDD (HIPCIDD) in sideband IPC (cAVS 1.8+)
21 * - DIPCTE in cAVS 1.5 IPC
28 /* Target, 0 - normal message, 1 - compact message(cAVS compatible) */
30 /* Direction, 0 - request, 1 - response */
41 /* Disable DMA tracing (0 - keep tracing, 1 - to disable DMA trace) */
43 /* Prevent clock gating (0 - cg allowed, 1 - DSP clock always on) */
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/linux/drivers/net/phy/
H A Dphy-c45.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include "mdio-open-alliance.h"
12 #include "phylib-internal.h"
15 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
22 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able()
27 phydev->pma_extable = val; in genphy_c45_baset1_able()
30 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able()
34 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
49 * genphy_c45_pma_resume - wakes up the PMA module
55 return -EOPNOTSUPP; in genphy_c45_pma_resume()
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/linux/drivers/clk/tegra/
H A Dclk-dfll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-dfll.c - Tegra DFLL clock source common code
5 * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
12 * "CL-DVFS". To try to avoid confusion, this code refers to them
18 * DFLL can be operated in either open-loop mode or closed-loop mode.
19 * In open-loop mode, the DFLL generates an output clock appropriate
20 * to the supply voltage. In closed-loop mode, when configured with a
27 * performance-measurement code and any code that relies on the CPU
32 #include <linux/clk-provider.h>
49 #include "clk-dfll.h"
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/linux/drivers/net/wireless/realtek/rtw88/
H A Dregd.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
19 const struct rtw_regd *__r = &__d->regd; \
23 __r->regulatory->alpha2[0], \
24 __r->regulatory->alpha2[1], \
25 __r->regulatory->txpwr_regd_2g, \
26 __r->regulatory->txpwr_regd_5g, \
27 __r->dfs_region); \
76 COUNTRY_REGD_ENT("CG", RTW_REGD_ETSI, RTW_REGD_ETSI),
283 struct rtw_dev *rtwdev = hw->priv; in rtw_regd_apply_hw_cap_flags()
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/linux/drivers/net/wireless/realtek/rtw89/
H A Dregd.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
171 COUNTRY_REGD("CG", RTW89_ETSI, RTW89_ETSI, RTW89_ETSI, 0x0),
272 static const char rtw89_alpha2_list_eu[][3] = {
310 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; in rtw89_regd_find_reg_by_name()
311 const struct rtw89_regd_ctrl *regd_ctrl = &regulatory->ctrl; in rtw89_regd_find_reg_by_name()
314 for (i = 0; i < regd_ctrl->nr; i++) { in rtw89_regd_find_reg_by_name()
315 if (!memcmp(regd_ctrl->map[i].alpha2, alpha2, 2)) in rtw89_regd_find_reg_by_name()
316 return &regd_ctrl->map[i]; in rtw89_regd_find_reg_by_name()
329 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; in rtw89_regd_get_index()
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/linux/drivers/gpu/drm/amd/pm/swsmu/
H A Damdgpu_smu.c2 * Copyright 2019 Advanced Micro Devices, Inc.
89 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) in smu_sys_get_pp_feature_mask()
90 return -EOPNOTSUPP; in smu_sys_get_pp_feature_mask()
100 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) in smu_sys_set_pp_feature_mask()
101 return -EOPNOTSUPP; in smu_sys_set_pp_feature_mask()
108 if (!smu->ppt_funcs->set_gfx_off_residency) in smu_set_residency_gfxoff()
109 return -EINVAL; in smu_set_residency_gfxoff()
116 if (!smu->ppt_funcs->get_gfx_off_residency) in smu_get_residency_gfxoff()
117 return -EINVAL; in smu_get_residency_gfxoff()
124 if (!smu->ppt_funcs->get_gfx_off_entrycount) in smu_get_entrycount_gfxoff()
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