Lines Matching +full:3 +full:cg +full:- +full:2019

1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
6  * Copyright(c) 2019 Intel Corporation
16  * - DIPCTDR (HIPCIDR) in sideband IPC (cAVS 1.8+)
17  * - DIPCT in cAVS 1.5 IPC
20  * - DIPCTDD (HIPCIDD) in sideband IPC (cAVS 1.8+)
21  * - DIPCTE in cAVS 1.5 IPC
28 /* Target, 0 - normal message, 1 - compact message(cAVS compatible) */
30 /* Direction, 0 - request, 1 - response */
41 /* Disable DMA tracing (0 - keep tracing, 1 - to disable DMA trace) */
43 /* Prevent clock gating (0 - cg allowed, 1 - DSP clock always on) */
44 #define HDA_PM_PCG		BIT(3)
45 /* Prevent power gating (0 - deep power state transitions allowed) */