| /linux/drivers/net/ethernet/marvell/octeontx2/nic/ |
| H A D | otx2_reg.h | 16 #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3) argument
18 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3) argument
19 #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3) argument
20 #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3) argument
21 #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3) argument
22 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3) argument
23 #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3) argument
24 #define RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) (0x8C0 | (a) << 3) argument
25 #define RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) (0x8E0 | (a) << 3) argument
26 #define RVU_PF_VFFLR_INTX(a) (0x900 | (a) << 3) argument
[all …]
|
| /linux/Documentation/networking/device_drivers/ethernet/3com/ |
| H A D | vortex.rst | 4 3Com Vortex device driver
12 This document describes the usage and errata of the 3Com "Vortex" device
13 driver for Linux, 3c59x.c.
29 3c575-series Cardbus cards which used to be handled by 3c575_cb.c.
33 - 3c590 Vortex 10Mbps
34 - 3c592 EISA 10Mbps Demon/Vortex
35 - 3c597 EISA Fast Demon/Vortex
36 - 3c595 Vortex 100baseTx
37 - 3c595 Vortex 100baseT4
38 - 3c595 Vortex 100base-MII
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|
| /linux/tools/perf/pmu-events/arch/x86/ivytown/ |
| H A D | uncore-power.json | 4 "Counter": "0,1,2,3",
7 …a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the counter was…
12 "Counter": "0,1,2,3",
21 "Counter": "0,1,2,3",
30 "Counter": "0,1,2,3",
39 "Counter": "0,1,2,3",
48 "Counter": "0,1,2,3",
57 "Counter": "0,1,2,3",
66 "Counter": "0,1,2,3",
75 "Counter": "0,1,2,3",
[all …]
|
| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-rgb.rst | 10 These formats encode each pixel as a triplet of RGB values. They are packed
13 bits required to store a pixel is not aligned to a byte boundary, the data is
21 or a permutation thereof, collectively referred to as alpha formats) depend on
25 a meaningful value. Otherwise, when the device doesn't capture an alpha channel
26 but can set the alpha bit to a user-configurable value, the
29 the value specified by that control. Otherwise a corresponding format without
35 filled with meaningful values by applications. Otherwise a corresponding format
39 Formats that contain padding bits are named XRGB (or a permutation thereof).
45 - In all the tables that follow, bit 7 is the most significant bit in a byte.
47 respectively. 'a' denotes bits of the alpha component (if supported by the
[all …]
|
| /linux/drivers/iio/accel/ |
| H A D | Kconfig | 18 To compile this driver as a module, say M here: the module will
30 To compile this driver as a module, say M here: the module will be
37 tristate "Analog Devices ADXL313 3-Axis Digital Accelerometer I2C Driver"
43 ADXL313 3-axis digital accelerometer.
45 To compile this driver as a module, choose M here: the module
50 tristate "Analog Devices ADXL313 3-Axis Digital Accelerometer SPI Driver"
56 ADXL313 3-axis digital accelerometer.
58 To compile this driver as a module, choose M here: the module
66 tristate "Analog Devices ADXL345 3-Axis Digital Accelerometer I2C Driver"
73 ADXL345 or ADXL375 3-axis digital accelerometer.
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/haswellx/ |
| H A D | uncore-power.json | 4 "Counter": "0,1,2,3",
7 …a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the counter was…
12 "Counter": "0,1,2,3",
21 "Counter": "0,1,2,3",
30 "Counter": "0,1,2,3",
39 "Counter": "0,1,2,3",
48 "Counter": "0,1,2,3",
57 "Counter": "0,1,2,3",
66 "Counter": "0,1,2,3",
75 "Counter": "0,1,2,3",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | uncore-power.json | 4 "Counter": "0,1,2,3",
7 …a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was e…
12 "Counter": "0,1,2,3",
21 "Counter": "0,1,2,3",
30 "Counter": "0,1,2,3",
39 "Counter": "0,1,2,3",
48 "Counter": "0,1,2,3",
57 "Counter": "0,1,2,3",
66 "Counter": "0,1,2,3",
75 "Counter": "0,1,2,3",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | uncore-power.json | 4 "Counter": "0,1,2,3",
7 …a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was e…
12 "Counter": "0,1,2,3",
21 "Counter": "0,1,2,3",
30 "Counter": "0,1,2,3",
39 "Counter": "0,1,2,3",
48 "Counter": "0,1,2,3",
57 "Counter": "0,1,2,3",
66 "Counter": "0,1,2,3",
75 "Counter": "0,1,2,3",
[all …]
|
| H A D | memory.json | 4 "Counter": "0,1,2,3",
14 "Counter": "0,1,2,3",
17 "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
23 "Counter": "0,1,2,3",
32 "Counter": "0,1,2,3",
35 "PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
41 "Counter": "0,1,2,3",
44 "PublicDescription": "Number of times HLE caused a fault.",
50 "Counter": "0,1,2,3",
53 "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3
30 { global() object
[all...] |
| /linux/lib/crypto/x86/ |
| H A D | sha1-ssse3-and-avx.S | 3 * This is a SIMD SHA-1 implementation. It requires the Intel(R) Supplemental
61 /* we keep window of 64 w[i]+K pre-calculated values in a circular buffer */
113 mov (HASH_PTR), A
127 RR F1,A,B,C,D,E,0
128 RR F1,D,E,A,B,C,2
129 RR F1,B,C,D,E,A,4
130 RR F1,E,A,B,C,D,6
131 RR F1,C,D,E,A,B,8
133 RR F1,A,B,C,D,E,10
134 RR F1,D,E,A,B,C,12
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|
| /linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
12 …"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unav…
13 "Counter": "0,1,2,3",
16 …"PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (…
21 …"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unav…
22 "Counter": "0,1,2,3",
27 …"PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (…
32 …"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 res…
33 "Counter": "0,1,2,3",
36 …"PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack o…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/icelake/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
12 …"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unav…
13 "Counter": "0,1,2,3",
16 …"PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (…
21 …"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unav…
22 "Counter": "0,1,2,3",
27 …"PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (…
32 …"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 res…
33 "Counter": "0,1,2,3",
36 …"PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack o…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/skylake/ |
| H A D | virtual-memory.json | 4 "Counter": "0,1,2,3",
7 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
13 "Counter": "0,1,2,3",
21 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
22 "Counter": "0,1,2,3",
26 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
32 "Counter": "0,1,2,3",
35 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
40 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | virtual-memory.json | 4 "Counter": "0,1,2,3",
7 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
13 "Counter": "0,1,2,3",
21 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
22 "Counter": "0,1,2,3",
26 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
32 "Counter": "0,1,2,3",
35 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
40 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| H A D | virtual-memory.json | 4 "Counter": "0,1,2,3",
7 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
13 "Counter": "0,1,2,3",
21 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
22 "Counter": "0,1,2,3",
26 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
32 "Counter": "0,1,2,3",
35 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
40 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/westmereep-sp/ |
| H A D | cache.json | 84 "Counter": "0,1,2,3",
92 "Counter": "0,1,2,3",
100 "Counter": "0,1,2,3",
108 "Counter": "0,1,2,3",
116 "Counter": "0,1,2,3",
124 "Counter": "0,1,2,3",
132 "Counter": "0,1,2,3",
140 "Counter": "0,1,2,3",
148 "Counter": "0,1,2,3",
156 "Counter": "0,1,2,3",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/graniterapids/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
12 "Counter": "0,1,2,3",
20 "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
21 "Counter": "0,1,2,3",
24 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
29 "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
30 "Counter": "0,1,2,3",
35 "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
40 "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
41 "Counter": "0,1,2,3",
28 { global() object
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/alderlake/ |
| H A D | virtual-memory.json | 4 "Counter": "0,1,2,3",
13 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
14 "Counter": "0,1,2,3",
18 "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
25 "Counter": "0,1,2,3,4,5",
34 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
35 "Counter": "0,1,2,3",
38 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a faul
33 { global() object
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
7 "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's cache, after the data is forwarded back to the requestor and indicating the data was found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single snoop response from the core counts on all hyperthreads of the core.",
13 "Counter": "0,1,2,3",
16 "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's caches, after the data is forwarded back to the requestor, and indicating the data was found modified(M) in this cores caches cache (aka HitM response). A single snoop response from the core counts on all hyperthreads of the core.",
22 "Counter": "0,1,2,3",
25 "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated in this core's caches without forwarded back to the requestor. The line was in Forward, Shared or Exclusive (FSE) state in this cores caches. A single snoop response from the core counts on all hyperthreads of the core.",
31 "Counter": "0,1,2,3",
34 "PublicDescription": "Counts responses to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop response from the core counts on all hyperthreads of the Core.",
40 "Counter": "0,1,2,3",
43 "PublicDescription": "Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (FS) Forward or Shared state. A singl
29 { global() object
[all...] |
| /linux/drivers/net/ethernet/3com/ |
| H A D | Kconfig | 3 # 3Com Ethernet device configuration
7 bool "3Com devices"
11 If you have a network (Ethernet) card belonging to this class, say Y.
15 the questions about 3Com cards. If you say Y, you will be asked for
21 tristate "3c509/3c579 \"EtherLink III\" support"
24 If you have a network (Ethernet) card belonging to the 3Com
31 To compile this driver as a module, choose M here. The module
32 will be called 3c509.
35 tristate "3c590/3c900 series (592/595/597) \"Vortex/Boomerang\" support"
39 This option enables driver support for a large number of 10Mbps and
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/meteorlake/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.",
4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3",
22 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
23 "Counter": "0,1,2,3",
27 "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a deman
32 { global() object
[all...] |
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
14 "Counter": "0,1,2,3",
17 "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
24 "Counter": "0,1,2,3",
27 "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 1
32 { global() object
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/arrowlake/ |
| H A D | virtual-memory.json | 3 …"BriefDescription": "Counts the number of page walks initiated by a demand load that missed the fi…
4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
21 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
22 "Counter": "0,1,2,3,4,5,6,7",
31 "Counter": "0,1,2,3,4,5,6,7,8,9",
40 …s but second level hits due to a demand load that did not start a page walk. Accounts for all page…
41 "Counter": "0,1,2,3,4,5,6,7",
49 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
50 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
|
| H A D | frontend.json | 4 "Counter": "0,1,2,3,4,5,6,7",
7 "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
24 "Counter": "0,1,2,3,4,5,6,7",
27 "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
33 "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
34 "Counter": "0,1,2,3,
32 { global() object
[all...] |
| /linux/Documentation/admin-guide/thermal/ |
| H A D | intel_powerclamp.rst | 34 Consider the situation where a system’s power consumption must be
70 If the kernel can also inject idle time to the system, then a
72 level C-state. The intel_powerclamp driver is conceived as such a
73 control system, where the target set point is a user-selected idle
84 of jiffies, so accumulated errors can be prevented to avoid a jittery
92 values. This effect can be better visualized using a Perf timechart.
95 for a given "duration", then relinquishes the CPU to other tasks,
100 have a dramatic impact on the effectiveness of the powerclamp driver
121 this document. The controlling CPU is elected at runtime, with a
122 policy that favors BSP, taking into account the possibility of a CPU
[all …]
|