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/linux/Documentation/fb/
H A Dviafb.modes14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
30 geometry 640 480 640 480 32
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
39 # Scan Frequency 37.500 kHz 75.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
60 # Scan Frequency 43.269 kHz 85.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
[all …]
/linux/drivers/video/fbdev/core/
H A Dmodedb.c39 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
43 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
44 { NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2, 0,
47 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
51 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
55 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
56 { NULL, 85, 640, 400, 31746, 96, 32, 41, 1, 64, 3,
59 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
63 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
67 /* 800x600 @ 60 Hz, 37.8 kHz hsync */
[all …]
/linux/arch/arm/mach-omap1/
H A Dtimer32k.c4 * OMAP 32K Timer
59 * 32KHz OS timer
62 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
63 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
65 * with the 32KHz synchronized timer.
129 .name = "32k-timer",
152 IRQF_TIMER | IRQF_IRQPOLL, "32KHz timer", NULL)) in omap_init_32k_timer()
153 pr_err("Failed to request irq %d(32KHz timer)\n", INT_OS_TIMER); in omap_init_32k_timer()
160 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
167 * 32KHz clocksource ... always available, on pretty most chips except
[all …]
/linux/Documentation/arch/arm/sunxi/
H A Dclocks.rst18 24MHz 32kHz
26 When you are about to suspend, you switch the CPU Mux to the 32kHz
29 24Mhz 32kHz
39 32kHz
/linux/include/sound/
H A Ddesignware_i2s.h15 * @data_width: number of bits per sample (8/16/24/32 bit)
16 * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz)
/linux/sound/ppc/
H A Dawacs.h112 #define SAMPLERATE_48000 (0x0 << 3) /* 48 or 44.1 kHz */
113 #define SAMPLERATE_32000 (0x1 << 3) /* 32 or 29.4 kHz */
114 #define SAMPLERATE_24000 (0x2 << 3) /* 24 or 22.05 kHz */
115 #define SAMPLERATE_19200 (0x3 << 3) /* 19.2 or 17.64 kHz */
116 #define SAMPLERATE_16000 (0x4 << 3) /* 16 or 14.7 kHz */
117 #define SAMPLERATE_12000 (0x5 << 3) /* 12 or 11.025 kHz */
118 #define SAMPLERATE_9600 (0x6 << 3) /* 9.6 or 8.82 kHz */
119 #define SAMPLERATE_8000 (0x7 << 3) /* 8 or 7.35 kHz */
172 #define RATE_48000 (0x0 << 8) /* 48 kHz */
173 #define RATE_44100 (0x0 << 8) /* 44.1 kHz */
[all …]
/linux/drivers/media/dvb-frontends/
H A Dmxl5xx_defs.h144 /* macro to extract a single byte from 4-byte(32-bit) data */
149 #define MXL_GET_REG_MASK_32(lsb_loc, num_of_bits) ((0xFFFFFFFF >> (32 - (num_of_bits))) << (lsb_loc…
396 MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */
397 MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */
398 MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */
399 MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */
401 MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */
402 MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, /* 204.35 KHz for 27 MHz XTAL */
403 MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, /* 306.52 KHz for 27 MHz XTAL */
404 MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, /* 408.69 KHz for 27 MHz XTAL */
[all …]
/linux/arch/mips/alchemy/common/
H A Dtime.c16 * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
32 /* 32kHz clock enabled and detected */
43 .mask = CLOCKSOURCE_MASK(32),
82 /* Check if firmware (YAMON, ...) has enabled 32kHz and clock in alchemy_time_init()
86 * (the 32S bit seems to be stuck set to 1 once a single clock- in alchemy_time_init()
101 alchemy_wrsys(0, AU1000_SYS_RTCTRIM); /* 32.768 kHz */ in alchemy_time_init()
119 cd->shift = 32; in alchemy_time_init()
/linux/drivers/cpufreq/
H A Dgx-suspmod.c28 * 32us intervals which the SUSP# pin is asserted(ON)/de-asserted(OFF)
90 #define PCI_MODOFF 0x94 /* suspend modulation OFF counter register, 1 = 32us */
128 * (32us * MAX_DURATION). If no parameter is given, this defaults
132 * though. 781.25 kHz(!) for a 200 MHz processor -- wow. */
217 static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration, in gx_validate_speed() argument
229 tmp_off = ((khz * i) / stock_freq) & 0xff; in gx_validate_speed()
232 /* if this relation is closer to khz, use this. If it's equal, in gx_validate_speed()
234 if (abs(tmp_freq - khz) <= abs(old_tmp_freq - khz)) { in gx_validate_speed()
247 * set cpu speed in khz.
250 static void gx_set_cpuspeed(struct cpufreq_policy *policy, unsigned int khz) in gx_set_cpuspeed() argument
[all …]
/linux/sound/pci/ca0106/
H A Dca0106.h144 * bit 12 0 = 48 Khz / 1 = 96 Khz Analog out on SB Live 24bit.
203 * Playback rate [23:16] (2 bits per channel) (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
232 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
233 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
234 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
335 …ne ROUTING1_REAR 0x77000000 /* Channel_id 0 sends to 10, Channel_id 1 sends to 32 */
407 /* Estimated sample rate [19:0] Relative to 48kHz. 0x8000 = 1.0
416 * Sample output rate [1:0] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
417 * Sample input rate [3:2] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
419 * Record rate [9:8] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun55i-a523-ccu.yaml56 - description: Low Frequency Oscillator (usually at 32kHz)
78 - description: Low Frequency Oscillator (usually at 32kHz)
110 - description: Low Frequency Oscillator (usually at 32kHz)
H A Dclk-palmas-clk32kg-clocks.txt1 * Palmas 32KHz clocks *
3 Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
/linux/drivers/media/tuners/
H A Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
41 1a d0 set frequency: 125 kHz scale, n*125 kHz
65 #define QT1010_STEP (125 * kHz) /*
/linux/arch/arm/mach-rockchip/
H A Dpm.c75 * function of usb wakeup, so do not switch to 32khz, since the usb phy in rk3288_slp_disable_osc()
76 * clk does not connect to 32khz osc in rk3288_slp_disable_osc()
142 * switch its main clock supply to the alternative 32kHz in rk3288_slp_mode_set()
143 * source. Therefore set 30ms on a 32kHz clock for pmic in rk3288_slp_mode_set()
147 regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30); in rk3288_slp_mode_set()
151 osc_disable ? 32 * 30 : 0); in rk3288_slp_mode_set()
/linux/Documentation/ABI/testing/
H A Dsysfs-class-rtc-rtc0-device-rtc_calibration7 calibrate the AB8500.s 32KHz Real Time Clock.
12 30.5 micro-seconds (half-parts-per-million of the 32KHz clock)
/linux/drivers/clocksource/
H A Dtimer-ep93xx.c27 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
28 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
31 * The 508 kHz timers are ideal for use for the timer interrupt, as the
32 * most common values of HZ divide 508 kHz nicely. We pick the 32 bit
91 /* Default mode: periodic, off, 508 kHz */ in ep93xx_clkevt_set_next_event()
/linux/Documentation/sound/cards/
H A Dhdspm.rst37 * Double Speed -- 1..32 channels
42 over the MADI, but all 32 channels are available for the mixer,
54 * Format -- signed 32 Bit Little Endian (SNDRV_PCM_FMTBIT_S32_LE)
143 * Values -- "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
144 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
145 "Internal 96.0 kHz"
/linux/Documentation/hwmon/
H A Dg760a.rst24 cycle counts of an assumed 32kHz clock source.
30 from the measured speed pulse period by assuming again a 32kHz clock
/linux/drivers/gpu/drm/radeon/
H A Datombios.h445 ULONG ulClockFreq:24; // in unit of 10kHz
447 ULONG ulClockFreq:24; // in unit of 10kHz
584 ULONG ulTargetEngineClock; //In 10Khz unit
589 ULONG ulTargetEngineClock; //In 10Khz unit
598 ULONG ulTargetMemoryClock; //In 10Khz unit
603 ULONG ulTargetMemoryClock; //In 10Khz unit
612 ULONG ulDefaultEngineClock; //In 10Khz unit
613 ULONG ulDefaultMemoryClock; //In 10Khz unit
676 USHORT usPixelClock; // in 10KHz; for bios convenient
692 USHORT usPixelClock; // in 10KHz; for bios convenient
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Datombios.h479 ULONG ulClockFreq:24; // in unit of 10kHz
481 ULONG ulClockFreq:24; // in unit of 10kHz
687 ULONG ulTargetEngineClock; //In 10Khz unit
692 ULONG ulTargetEngineClock; //In 10Khz unit
698 ULONG ulTargetEngineClock; //In 10Khz unit
708 ULONG ulTargetMemoryClock; //In 10Khz unit
713 ULONG ulTargetMemoryClock; //In 10Khz unit
722 ULONG ulDefaultEngineClock; //In 10Khz unit
723 ULONG ulDefaultMemoryClock; //In 10Khz unit
740 ASIC_INIT_CLOCK_PARAMETERS asSclkClock; //In 10Khz unit
[all …]
/linux/arch/arm/mach-pxa/
H A Dgumstix.c131 /* Normally, the bootloader would have enabled this 32kHz clock but many
139 pr_warn("32kHz clock was not on. Bootloader may need to be updated\n"); in gumstix_setup_bt_clock()
150 pr_err("Failed to start 32kHz clock\n"); in gumstix_setup_bt_clock()
/linux/Documentation/devicetree/bindings/rtc/
H A Dingenic,rtc.yaml68 (assuming RTC clock at 32 kHz)
76 (assuming RTC clock at 32 kHz)
108 interrupts = <32>;
/linux/sound/soc/codecs/
H A Dmax98363.c65 .reg_bits = 32,
146 for_each_set_bit(bit, &addr, 32) { in max98363_read_prop()
327 "Reserved", "0", "+FS/2", "-FS/2", "1KHz",
328 "12KHz", "8KHz", "6KHz", "4KHz", "3KHz",
329 "2KHz", "1.5KHz", "Reserved", "500Hz", "250Hz"
/linux/sound/firewire/dice/
H A Ddice.c102 char vendor[32], model[32]; in dice_card_strings()
395 // Weiss DAC202: 192kHz 2-channel DAC
402 // Weiss DAC202: 192kHz 2-channel DAC (Maya edition)
409 // Weiss MAN301: 192kHz 2-channel music archive network player
416 // Weiss INT202: 192kHz unidirectional 2-channel digital Firewire face
423 // Weiss INT203: 192kHz bidirectional 2-channel digital Firewire face
430 // Weiss ADC2: 192kHz A/D converter with microphone preamps and inputs
437 // Weiss DAC2/Minerva: 192kHz 2-channel DAC
444 // Weiss Vesta: 192kHz 2-channel Firewire to AES/EBU interface
451 // Weiss AFI1: 192kHz 24-channel Firewire to ADAT or AES/EBU face
/linux/drivers/i2c/busses/
H A Di2c-sis630.c19 | Clock | 14kHz/56kHz | 55.56kHz/27.78kHz |
96 "Set Host Master Clock to 56KHz (default 14KHz) (SIS630/730 only).");
148 * set Host Master Clock to 56KHz if requested */ in sis630_transaction_start()
206 * and oldclock was not 56KHz in sis630_transaction_end()
239 else if (len > 32) in sis630_block_data()
240 len = 32; in sis630_block_data()
296 if (data->block[0] > 32) in sis630_block_data()
297 data->block[0] = 32; in sis630_block_data()

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