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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dlpc1850-creg-clk.txt5 32 kHz oscillator driver with power up/down and clock gating. Next
6 is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
9 The 32 kHz can also be routed to other peripherals to enable low
21 Shall contain a phandle to the fixed 32 kHz crystal.
28 0 1 kHz cloc
[all...]
H A Damlogic,gxbb-aoclkc.txt19 * "ext-32k-0" : external 32kHz reference #0 if any (optional)
20 * "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only)
21 * "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only)
H A Dmaxim,max77686.txt1 Binding for Maxim MAX77686/MAX77802/MAX77620 32k clock generator block
10 The MAX77686 contains three 32.768khz clock outputs that can be controlled
15 The MAX77802 contains two 32.768khz clock outputs that can be controlled
19 The MAX77686 contains one 32.768khz clock outputs that can be controlled
34 - 0: 32khz_ap clock (max77686, max77802), 32khz_out0 (max77620)
35 - 1: 32khz_cp clock (max77686, max77802),
36 - 2: 32khz_pmic clock (max77686).
H A Dclk-palmas-clk32kg-clocks.txt1 * Palmas 32KHz clocks *
3 Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
H A Dsamsung,s2mps11.txt8 The S2MPS11/13/15 and S5M8767 provide three(AP/CP/BT) buffered 32.768 kHz
9 outputs. The S2MPS14 provides two (AP/BT) buffered 32.768 KHz outputs.
30 32KhzAP 0 S2MPS11/13/14/15, S5M8767
31 32KhzCP 1 S2MPS11/13/15, S5M8767
32 32KhzBT 2 S2MPS11/13/14/15, S5M8767
H A Dstericsson,u8500-clks.yaml17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
92 description: A subnode with zero clock cells for the 32kHz RTC clock.
/freebsd/contrib/file/magic/scripts/
H A Dcreate_filemagic_flac6 ## >>17 belong&0xfffff0 0x2ee000 \b, 192 kHz
15 ## (16384 kHz = 32 kHz * 512 = 32 * 2^9)
17 ## (22579.2 kHz = 44.1kHz * 512 = 44.1 * 2^9)
20 ## (24576 kHz = 48 kHz * 512 = 48 * 2^9)
53 ## use bc with sed to convert and format Hz to kHz
58 printf -v line ">>17\tbelong&%#-15x\t%#08x\t%s, %s kHz\n" \
/freebsd/sys/dev/ath/ath_hal/ar5312/
H A Dar5312_misc.c92 * If 32KHz clock exists, use it to lower power consumption during sleep
94 * Note: If clock is set to 32 KHz, delays on accessing certain
103 * and also enable turning OFF 32MHz/40MHz Refclk in ar5312SetupClock()
115 OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */ in ar5312SetupClock()
118 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */ in ar5312SetupClock()
139 * If 32KHz clock exists, turn it off and turn back on the 32Mhz
145 /* # Set sleep clock rate back to 32 MHz. */ in ar5312RestoreClock()
146 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */ in ar5312RestoreClock()
/freebsd/contrib/file/magic/Magdir/
H A Daudio20 >12 belong 5 32-bit linear PCM,
22 >12 belong 6 32-bit IEEE floating point,
31 >12 belong 14 32-bit fixed point,
58 >12 lelong 5 32-bit linear PCM,
60 >12 lelong 6 32-bit IEEE floating point,
69 >12 belong 14 32-bit fixed point,
244 1080 string 32CN 32-channel Taketracker module sound data
303 >22 byte =0 replay 5.485 KHz
304 >22 byte =1 replay 8.084 KHz
305 >22 byte =2 replay 10.971 KHz
[all …]
H A Danimation343 >>>>10 byte&0xF0 32 \b, still texture
349 >>>9 byte&0xF8 32 \b, face
412 >>>5 byte&0xF0 32 \b, still texture (missing profile header)
418 >>4 byte&0xF8 32 \b, face (missing profile header)
545 >>>2 byte&0xF0 0x10 \b, 32 kbps
560 >>>2 byte&0x0C 0x00 \b, 44.1 kHz
561 >>>2 byte&0x0C 0x04 \b, 48 kHz
562 >>>2 byte&0x0C 0x08 \b, 32 kHz
580 >2 byte&0xF0 0x10 \b, 32 kbps
595 >2 byte&0x0C 0x00 \b, 44.1 kHz
[all …]
H A Ddolby13 >4 byte&0xc0 = 0x00 48 kHz,
14 >4 byte&0xc0 = 0x40 44.1 kHz,
15 >4 byte&0xc0 = 0x80 32 kHz,
16 # is this one used for 96 kHz?
51 >4 byte&0x3e = 0x00 \b, 32 kbit/s
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmax77620.txt36 with internal regulators. 32KHz clock can be programmed to be part of a
46 Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power
54 When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
58 and 32KHz clock get disabled at
68 regulators, GPIOs and 32kHz clocks are provided in their respective
H A Dmxs-lradc.txt15 Allowed value is 1 ... 32, default is 4
18 2 kHz and its default is 2 (= 1 ms)
20 1 ... 2047. It counts at 2 kHz and its default is
H A Dmax77802.txt4 efficiency Buck regulators, 32 Low-DropOut (LDO) regulators used to power
5 up application processors and peripherals, a 2-channel 32kHz clock outputs,
9 Bindings for the built-in 32k clock generator block and
/freebsd/share/man/man4/
H A Dsnd_hdsp.469 (32kHz-48kHz) and 4 channels at double speed (64kHz-96kHz).
70 Only the HDSP 9632 can operate at quad speed (128kHz-192kHz), ADAT is
107 The number of samples processed per interrupt, from 32, 64, 128, up to 4096.
H A Dsnd_hdspe.468 (32kHz-48kHz), 4 channels at double speed (64kHz-96kHz), and 2 channels at
69 quad speed (128kHz-192kHz).
105 The number of samples processed per interrupt, from 32, 64, 128, up to 4096.
H A Dsnd_emu10kx.478 PCM support is limited to 48kHz/16 bit stereo (192kHz/24 bit part
83 to 48kHz/16 bit stereo (192kHz/24 bit part of this chipset is not supported).
138 you will get one more DSP device that is rate-locked to 48kHz/16bit/mono.
139 This is actually 48kHz/16bit/32 channels on SB Live! cards and
140 48kHz/16bit/64channels on Audigy cards, but the current implementation of
145 outputs, the second half (15-30 or 32-63) is a copy of some DSP inputs.
/freebsd/sys/contrib/device-tree/Bindings/rtc/
H A Dingenic,rtc.yaml68 (assuming RTC clock at 32 kHz)
76 (assuming RTC clock at 32 kHz)
108 interrupts = <32>;
H A Dtrivial-rtc.yaml23 # AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface
25 # AB-RTCMC-32.768kHz-EOZ9: Real Time Clock/Calendar Module with I2C Interface
35 # I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Drenesas,raa215300.yaml14 32-bit and 64-bit MCU and MPU applications. It supports DDR3, DDR3L, DDR4,
16 built-in Real-Time Clock (RTC), 32kHz crystal oscillator, and coin cell
66 /* 32.768kHz crystal */
/freebsd/sys/arm/freescale/imx/
H A Dimx_machdep.c100 * within the same cycle of the 32khz clock to reliably trigger the in imx_wdog_cpu_reset()
102 * happen in the same 32k clock cycle. in imx_wdog_cpu_reset()
109 /* Reset happens on the next tick of the 32khz clock, wait for it. */ in imx_wdog_cpu_reset()
H A Dimx6_snvs.c57 #define RTC_RESOLUTION_US (1000000 / 32768) /* 32khz clock */
60 * The RTC is a 47-bit counter clocked at 32KHz and organized as a 32.15
131 counter1 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32); in snvs_gettime()
133 counter2 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32); in snvs_gettime()
161 WR4(sc, SNVS_LPSRTCMR, (uint32_t)(sbt >> (SBT_LSB + 32))); in snvs_settime()
/freebsd/sys/contrib/device-tree/Bindings/input/
H A Diqs626a.yaml245 multipleOf: 32
284 1: 2 MHz (500 kHz)
285 2: 1 MHz (250 kHz)
286 3: 500 kHz (125 kHz)
400 3: 2 MHz (500 kHz)
569 multipleOf: 32
604 1: 2 MHz (500 kHz)
605 2: 1 MHz (250 kHz)
606 3: 500 kHz (125 kHz)
631 4: 32
/freebsd/sys/i386/i386/
H A Dgeode.c164 offset += (1LL << 32); in geode_cputicks()
170 * The GEODE watchdog runs from a 32kHz frequency. One period of that is
203 * We run MFGPT0 off the 32kHz frequency and prescale by 16384 giving a
220 /* Set up MFGPT0, 32khz, prescaler 16k, C2 event */ in cs5536_watchdog()
/freebsd/sys/contrib/device-tree/src/arm/synaptics/
H A Dberlin2q.dtsi35 /* kHz uV */
53 /* kHz uV */
71 /* kHz uV */
89 /* kHz uV */
255 ngpios = <32>;
273 ngpios = <32>;
291 ngpios = <32>;
309 ngpios = <32>;
555 ngpios = <32>;
616 ngpios = <32>;

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