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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td33 def sub_32 : SubRegIndex<32>;
98 [RegInfo<32,32,32>, RegInfo<64,64,64>]>;
102 def GPR : RegisterClass<"LoongArch", [GRLenVT], 32, (add
120 def GPRT : RegisterClass<"LoongArch", [GRLenVT], 32, (add
130 def F0 : LoongArchReg32<0, "f0", ["fa0"]>, DwarfRegNum<[32]>;
164 def F#I#_64 : LoongArchReg64<!cast<LoongArchReg32>("F"#I)>,
165 DwarfRegNum<[!add(I, 32)]>;
170 def FPR32 : RegisterClass<"LoongArch", [f32], 32, (sequence "F%u", 0, 31)>;
178 def CFR : RegisterClass<"LoongArch", [GRLenVT], 32, (sequence "FCC%u", 0, 7)> {
188 def FCSR : RegisterClass<"LoongArch", [i32], 32, (sequence "FCSR%u", 0, 3)>;
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H A DLoongArchFloatInstrFormats.td24 // suffixed with `_x[SD]` or `_64`, that will get trimmed before the mnemonics
27 string ret = deriveInsnMnemonic<!subst("_64", "",
34 class FPFmt2R<bits<32> op, dag outs, dag ins, string opnstr,
47 class FPFmt3R<bits<32> op, dag outs, dag ins, string opnstr,
62 class FPFmt4R<bits<32> op, dag outs, dag ins, string opnstr,
79 class FPFmt2RI12<bits<32> op, dag outs, dag ins, string opnstr,
94 class FPFmtFCMP<bits<32> op, dag outs, dag ins, string opnstr,
109 class FPFmtBR<bits<32> op, dag outs, dag ins, string opnstr,
123 class FPFmtFSEL<bits<32> op, dag outs, dag ins, string opnstr,
140 class FPFmtMOV<bits<32> op, dag outs, dag ins, string opnstr,
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/freebsd/crypto/openssl/doc/man3/
H A DOPENSSL_ia32cap.pod5 OPENSSL_ia32cap - the x86[_64] processor capabilities vector
13 OpenSSL supports a range of x86[_64] instruction set extensions. These
64 For example, in 32-bit application context clearing bit #26 at run-time
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Ddialog,da7219.yaml133 enum: ["32_64", "64_128", "128_256", "256_512"]
226 dlg,jack-det-rate = "32_64";
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8183-kukui-audio-da7219.dtsi30 dlg,jack-det-rate = "32_64";
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td25 // 32-bit sub-register, CSKYAsmParser will need to coerce a register number
27 def sub32_0 : SubRegIndex<32, 0>;
28 def sub32_32 : SubRegIndex<32, 32>;
86 def R32 : CSKYReg<32, "r32", ["r32"]>, DwarfRegNum<[32]>;
94 [(add (sequence "R%u", 0, 31)), (add (sequence "R%u", 1, 32))],
103 def F0_32 : CSKYFReg32<0, "fr0", ["vr0"]>, DwarfRegNum<[32]>;
137 def F#Index#_64 : CSKYFReg64<!cast<CSKYFReg32>("F"#Index#"_32")>,
138 DwarfRegNum<[!add(Index, 32)]>;
140 def F#Index#_128 : CSKYFReg128<!cast<CSKYFReg64>("F"#Index#"_64")>,
141 DwarfRegNum<[!add(Index, 32)]>;
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/freebsd/secure/lib/libcrypto/man/man3/
H A DOPENSSL_ia32cap.3140 OPENSSL_ia32cap \- the x86[_64] processor capabilities vector
148 OpenSSL supports a range of x86[_64] instruction set extensions. These
195 For example, in 32\-bit application context clearing bit #26 at run-time
/freebsd/usr.bin/clang/llvm-nm/
H A Dllvm-nm.1215 .B 32
216 Process only 32\-bit object files.
221 .B 32_64
222 Process both 32\-bit and 64\-bit object files.
230 On AIX OS, the default is to process 32\-bit object files only and to ignore
233 64\-bit objects and ignore 32\-bit objects. The \-X flag overrides the OBJECT_MODE
/freebsd/contrib/llvm-project/llvm/lib/Support/BLAKE3/
H A DREADME.md36 // Finalize the hash. Default output length is 32 bytes.
77 // Finalize the hash. LLVM_BLAKE3_OUT_LEN is the default output length, 32 bytes.
167 the default output length, 32 bytes, which is recommended for most
170 Outputs shorter than the default length of 32 bytes (256 bits) provide
189 exactly 32 bytes.
278 assembly versions are x86\_64-only, and you need to select the right
/freebsd/contrib/llvm-project/llvm/tools/llvm-nm/
H A DOpts.td16 def X : JoinedOrSeparate<["-"], "X">, HelpText<"Specifies the type of ELF, XCOFF, or IR object file to examine. The value must be one of: 32, 64, 32_64, any (default)">;
H A Dllvm-nm.cpp1707 // There is no visibility in old 32 bit XCOFF object file interpret. in getXCOFFExports()
2483 .Case("32", BitModeTy::Bit32) in llvm_nm_main()
2485 .Case("32_64", BitModeTy::Bit32_64) in llvm_nm_main()
2493 if (Mode == "32") in llvm_nm_main()
2497 else if (Mode == "32_64") in llvm_nm_main()
2502 error("-X value should be one of: 32, 64, 32_64, (default) any"); in llvm_nm_main()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td13 def sub_32 : SubRegIndex<32>;
15 def sub_lo : SubRegIndex<32>;
16 def sub_hi : SubRegIndex<32, 32>;
28 // We have banks of 32 registers each.
49 // Mips 32-bit FPU Registers
158 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
162 def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
173 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>,
174 DwarfRegNum<[!add(I, 32)]>;
179 def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>,
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H A DMipsInstrInfo.td64 // using static relocations with 64 bit symbols, or lui when using 32 bit
100 // Node used to insert 32-bit integers to LOHI register pair.
288 // subtractive predicate will hopefully keep us under the 32 predicate
629 let RenderMethod = "addConstantUImmOperands<32>";
649 // uimm5 < uimm5_plus1 (1..32) < uimm5_plus32 (32..63) < uimm6
664 : SImmAsmOperandClass<32, [UImm32CoercedAsmOperandClass]> {
670 : SImmAsmOperandClass<32, [SImm32RelaxedAsmOperandClass]>;
784 5, [ConstantUImm5ReportUImm6AsmOperandClass], 32>;
786 : ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus32AsmOperandClass], 32> {
788 // We must also subtract 32 when we render the operand.
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/freebsd/contrib/llvm-project/llvm/tools/llvm-ar/
H A Dllvm-ar.cpp72 << " -X{32|64|32_64|any} - Specify which archive symbol tables " in printRanLibHelp()
94 -X{32|64|32_64|any} - object mode (only for AIX OS) in printArHelp()
1288 .Case("32", BitModeTy::Bit32) in getBitMode()
1290 .Case("32_64", BitModeTy::Bit32_64) in getBitMode()
1485 "OBJECT_MODE must be 32, 64, 32_64, or any"); in ranlib_main()
/freebsd/usr.bin/clang/llvm-ar/
H A Dllvm-ar.1373 .B 32
374 Process only 32\-bit object files.
379 .B 32_64
380 Process both 32\-bit and 64\-bit object files.
388 The default is to process 32\-bit object files (ignore 64\-bit objects). The mode can also
390 process any 64\-bit objects and ignore 32\-bit objects. The \-X flag overrides the OBJECT_MODE
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_x86_64.h26 LLVM_EXTENSION offsetof(XSAVE, ymmh[0]) + (32 * reg_index))
97 RegisterContextPOSIX_x86::g_contained_##streg##_64, \
98 RegisterContextPOSIX_x86::g_invalidate_##streg##_64, \
H A DRegisterInfos_x86_64_with_base.h28 LLVM_EXTENSION offsetof(XSAVE, ymmh[0]) + (32 * reg_index))
96 RegisterInfos_x86_64_with_base_shared::g_contained_##streg##_64, \
97 RegisterInfos_x86_64_with_base_shared::g_invalidate_##streg##_64, \
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXIntrinsics.td347 def _64 : NVPTXInst<(outs), (ins Int64Regs:$addr),
367 def _64 : NVPTXInst<(outs), (ins Int64Regs:$dst, Int64Regs:$src),
445 def _64 : NVPTXInst<(outs), (ins Int64Regs:$addr, Int32Regs:$count),
460 def _64 : NVPTXInst<(outs), (ins Int64Regs:$addr),
475 def _64 : NVPTXInst<(outs Int64Regs:$state), (ins Int64Regs:$addr),
492 def _64 : NVPTXInst<(outs Int64Regs:$state),
511 def _64 : NVPTXInst<(outs Int64Regs:$state), (ins Int64Regs:$addr),
530 def _64 : NVPTXInst<(outs Int64Regs:$state),
549 def _64 : NVPTXInst<(outs Int1Regs:$res), (ins Int64Regs:$addr, Int64Regs:$state),
1701 defm INT_PTX_ATOM_SUB_G_32 : F_ATOMIC_2_NEG<i32, Int32Regs, ".global", "32", ".add",
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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3399-gru.dtsi452 dlg,jack-det-rate = "32_64";
699 &clk_32k /* This pin is always 32k on gru boards */
/freebsd/crypto/openssl/crypto/rc4/asm/
H A Drc4-586.pl18 # assembler implementation performs suboptimally on latest IA-32
356 # [including EM64T] was found to perform poorly with above "32-bit" key
357 # schedule, a.k.a. RC4_INT. Performance improvement for IA-32 hand-coded
360 # schedule for x86[_64], because non-P4 implementations suffer from
/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DMathExtras.h149 // NOTE: The following support functions use the _32/_64 extensions instead of
153 /// Return the high 32 bits of a 64 bit value.
155 return static_cast<uint32_t>(Value >> 32); in Hi_32()
158 /// Return the low 32 bits of a 64 bit value.
163 /// Make a 64-bit integer from a high / low pair of 32-bit integers.
165 return ((uint64_t)High << 32) | (uint64_t)Low; in Make_64()
176 if constexpr (N == 32) in isInt()
200 if constexpr (N == 32) in isUInt()
265 /// least significant bit with the remainder zero (32 bit version).
278 /// remainder zero (32 bit version.) Ex. isShiftedMask_32(0x0000FF00U) == true.
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/freebsd/crypto/openssl/crypto/modes/
H A Dgcm128.c40 V.hi = (V.hi>>1 )^((u64)T<<32); \
60 * "4-bit" version. And for gcc-generated x86[_64] code, "8-bit" version
192 Z.hi ^= (u64)rem_8bit[rem] << 32; in gcm_gmult_8bit()
202 v = (u32)(Z.hi >> 32); in gcm_gmult_8bit()
206 v = (u32)(Z.lo >> 32); in gcm_gmult_8bit()
285 Htable[j].hi = V.lo << 32 | V.lo >> 32; in gcm_init_4bit()
286 Htable[j].lo = V.hi << 32 | V.hi >> 32; in gcm_init_4bit()
321 Z.hi ^= (u64)rem_4bit[rem] << 32; in gcm_gmult_4bit()
339 Z.hi ^= (u64)rem_4bit[rem] << 32; in gcm_gmult_4bit()
352 v = (u32)(Z.hi >> 32); in gcm_gmult_4bit()
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/freebsd/crypto/openssl/crypto/aes/
H A Daes_x86core.c11 * This is experimental x86[_64] derivative. It assumes little-endian
14 * serves as reference C implementation for x86[_64] as well as some
70 /* 32 is common least cache-line size */ in prefetch256()
71 for (sum=0,i=0;i<256/sizeof(t[0]);i+=32/sizeof(t[0])) sum ^= t[i]; in prefetch256()
/freebsd/sys/netpfil/ipfw/
H A Dip_fw_table_algo.c602 for (cp = (uint32_t *)addr6; mask >= 32; mask -= 32) in ipv6_writemask()
605 *cp = htonl(mask ? ~((1 << (32 - mask)) - 1) : 0); in ipv6_writemask()
633 htonl(mlen ? ~((1 << (32 - mlen)) - 1) : 0); in tei_to_sockaddr_ent_addr()
636 if (mlen != 32) in tei_to_sockaddr_ent_addr()
680 if (mlen > 32) in ta_prepare_add_addr_radix()
792 if (mlen > 32) in ta_prepare_del_addr_radix()
908 * inv.mask4: 32 - mask
912 * 3) _64: 8
917 * [ 32][ 32]
1237 if (mask4 < 0 || mask4 > 32 || mask6 < 0 || mask6 > 128) in chash_parse_opts()
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/freebsd/crypto/libecc/
H A DREADME.md148 for word sizes 16 and 32 bits). This is due to an internal limitation of libecc
373 …hese (in the 'Project options' category). For instance, compiling libecc with a word size of 32 and
377 $ meson setup -Dwith_wordsize=32 -Dwith_debug=true builddir && cd builddir && meson dist
423 libecc supports 16, 32 and 64 bits word sizes. Though this word size is usually inferred during com…
443 5300 bits for 64-bit words, around 2650 bits for 32-bit words, and around 1300 bits for 16-bit word…
453 `WORDSIZE=64`, and one tries to compile the arithmetic tests with `WORDSIZE=32`, here is the error …
678 This SoC is built around a Cortex-A9 ARMv7-A 32-bit architecture.
707 chosen WORDSIZE (16, 32, 64), the compilation options (optimization for space `-Os` or speed `-O3`)…
734 **Note**: The Cortex-M0 case is a bit special in the ARM family. Since this MCU lacks a 32-bit x 32…
736 in poor performance with WORDSIZE=64 compared to WORDSIZE=32 (this might be explained by the callin…
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