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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFormats.td1 //===-- MicroMipsInstrFormats.td - microMIPS Inst Formats -*- tablegen -*--===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
40 // Base class for MicroMIPS 16-bit instructions.
47 field bits<16> Inst;
48 field bits<16> SoftFail = 0;
49 bits<6> Opcode = 0x0;
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H A DMicroMips32r6InstrFormats.td1 //=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
23 //===----------------------------------------------------------------------===//
31 //===----------------------------------------------------------------------===//
35 //===----------------------------------------------------------------------===//
38 bits<10> offset;
40 bits<16> Inst;
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H A DMipsInstrFormats.td1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
14 // opcode - operation code.
15 // rs - src reg.
16 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
17 // rd - dst reg, only used on 3 regs instr.
18 // shamt - only used on shift instructions, contains the shift amount.
19 // funct - combined with opcode field give us an operation code.
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H A DMips32r6InstrFormats.td1 //=- Mips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
37 //===----------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
43 class OPGROUP<bits<6> Val> {
44 bits<6> Value = Val;
65 class OPCODE2<bits<2> Val> {
66 bits<2> Value = Val;
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsa8540p.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 /delete-node/ &cpu0_opp_table;
10 /delete-node/ &cpu4_opp_table;
13 cpu0_opp_table: opp-table-cpu0 {
14 compatible = "operating-points-v2";
15 opp-shared;
17 opp-300000000 {
18 opp-hz = /bits/ 64 <300000000>;
19 opp-peak-kBps = <(300000 * 32)>;
21 opp-403200000 {
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLSXInstrFormats.td1 // LoongArchLSXInstrFormats.td - LoongArch LSX Instr Formats -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // opcode - operation code.
13 // vd/rd/cd - destination register operand.
14 // {r/v}{j/k} - source register operand.
15 // immN - immediate data operand.
17 //===----------------------------------------------------------------------===//
19 // 1RI13-type
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H A DLoongArchLASXInstrFormats.td1 // LoongArchLASXInstrFormats.td - LoongArch LASX Instr Formats - tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // opcode - operation code.
13 // xd/rd/cd - destination register operand.
14 // {r/x}{j/k} - source register operand.
15 // immN - immediate data operand.
17 //===----------------------------------------------------------------------===//
19 // 1RI13-type
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H A DLoongArchFloatInstrFormats.td1 // LoongArchFloatInstrFormats.td - LoongArch FP Instr Formats -*- tablegen -*-//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
10 // Describe LoongArch floating-point instructions format
12 // opcode - operation code.
13 // fd - destination register operand.
14 // {c/f}{j/k/a} - source register operand.
15 // immN - immediate data operand.
17 //===----------------------------------------------------------------------===//
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H A DLoongArchLBTInstrFormats.td1 // LoongArchLBTInstrFormats.td - LoongArch LBT Instr Formats -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // opcode - operation code.
13 // rd/sd - destination register operand.
14 // rj/rk/sj - source register operand.
15 // immN/ptr - immediate data operand.
23 //===----------------------------------------------------------------------===//
25 // 1R-type (no outs)
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H A DLoongArchInstrFormats.td1 //===- LoongArchInstrFormats.td - LoongArch Instr. Formats -*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // opcode - operation code.
13 // rd - destination register operand.
14 // r{j/k} - source register operand.
15 // immN - immediate data operand.
17 //===----------------------------------------------------------------------===//
22 field bits<32> Inst;
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/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A Dlldb-x86-register-enums.h1 //===-- lldb-x86-register-enums.h -------------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
128 k_num_gpr_registers_i386 = k_last_gpr_i386 - k_first_gpr_i386 + 1,
129 k_num_fpr_registers_i386 = k_last_fpr_i386 - k_first_fpr_i386 + 1,
130 k_num_avx_registers_i386 = k_last_avx_i386 - k_first_avx_i386 + 1,
131 k_num_mpx_registers_i386 = k_last_mpxc_i386 - k_first_mpxr_i386 + 1,
136 k_num_dbr_registers_i386 = k_last_dbr_i386 - k_first_dbr_i386 + 1,
176 lldb_r8d_x86_64, // Low 32 bits of r8
177 lldb_r9d_x86_64, // Low 32 bits of r9
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H A DInstructionUtils.h1 //===-- InstructionUtils.h --------------------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
20 // least significant bit (lsbit) of a 64-bit unsigned value.
21 static inline uint64_t Bits64(const uint64_t bits, const uint32_t msbit, in Bits64() argument
24 return (bits >> lsbit) & ((1ull << (msbit - lsbit + 1)) - 1); in Bits64()
28 // least significant bit (lsbit) of a 32-bit unsigned value.
29 static inline uint32_t Bits32(const uint32_t bits, const uint32_t msbit, in Bits32() argument
31 assert(msbit < 32 && lsbit <= msbit); in Bits32()
32 return (bits >> lsbit) & ((1u << (msbit - lsbit + 1)) - 1); in Bits32()
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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dxmmintrin.h1 /*===---- xmmintrin.h - SSE intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
36 __attribute__((__always_inline__, __nodebug__, __target__("sse,no-evex512"), \
40 __target__("mmx,sse,no-evex512"), __min_vector_width__(64)))
42 /// Adds the 32-bit float values in the low-order bits of the operands.
49 /// A 128-bit vector of [4 x float] containing one of the source operands.
50 /// The lower 32 bits of this operand are used in the calculation.
52 /// A 128-bit vector of [4 x float] containing one of the source operands.
53 /// The lower 32 bits of this operand are used in the calculation.
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H A Dia32intrin.h1 /* ===-------- ia32intrin.h ---------------------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
38 /// A 32-bit integer operand.
39 /// \returns A 32-bit integer containing the bit number.
55 /// A 32-bit integer operand.
56 /// \returns A 32-bit integer containing the bit number.
60 return 31 - __builtin_clz((unsigned int)__A); in __bsrd()
71 /// A 32-bit integer operand.
72 /// \returns A 32-bit integer containing the swapped bytes.
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H A Dmmintrin.h1 /*===---- mmintrin.h - MMX intrinsics --------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
26 __attribute__((__always_inline__, __nodebug__, __target__("mmx,no-evex512"), \
37 __target__("mmx,no-evex512")))
42 /// Constructs a 64-bit integer vector, setting the lower 32 bits to the
43 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
50 /// A 32-bit integer value.
51 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
52 /// parameter. The upper 32 bits are set to 0.
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H A Dbmi2intrin.h1 /*===---- bmi2intrin.h - BMI2 intrinsics -----------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
20 /// Copies the unsigned 32-bit integer \a __X and zeroes the upper bits
26 /// IF i < 32
36 /// The 32-bit source value to copy.
38 /// The lower 8 bits specify the bit number of the lowest bit to zero.
39 /// \returns The partially zeroed 32-bit value.
46 /// Deposit (scatter) low-order bits from the unsigned 32-bit integer \a __X
47 /// into the 32-bit result, according to the mask in the unsigned 32-bit
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrFormats.td1 //===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 def isR600 : Predicate<"Subtarget->getGeneration() <= AMDGPUSubtarget::R700">;
16 "Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">;
26 field bits<64> Inst;
30 bits<2> FlagOperandIdx = 0;
59 let TSFlags{8-7} = FlagOperandIdx;
72 //===----------------------------------------------------------------------===//
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVSymbolicOperands.td1 //===- SPIRVSymbolicOperands.td ----------------------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines symbolic/named operands for various SPIR-V instructions.
11 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
17 // - Category (Extension/Capability/BuiltIn/etc.)
18 // - Value (32-bit representation for binary emission)
19 // - Mnemonic (String representation for textual emission)
20 // - MinVersion
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/freebsd/share/man/man3/
H A Dqmath.331 .Nd fixed-point math library based on the
39 data types and APIs support fixed-point math based on the
66 .Bq 2, 4, 6, 8, 16, 32, 48
67 bits of precision after the binary radix point,
72 The number of bits available for the integral component is not explicitly
73 specified, and implicitly consumes the remaining available bits of the chosen Q
79 None of the operations is affected by the floating-point environment.
86 .Bl -column "isgreaterequal" "bessel function of the second kind of the order 0"
124 .Xr Q_PRECEQ 3 compare bits
134 .Ss Functions which manipulate the control/sign data bits
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/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-h616-cpu-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 cpu_opp_table: opp-table-cpu {
6 compatible = "allwinner,sun50i-h616-operating-points";
7 nvmem-cells = <&cpu_speed_grade>;
8 opp-shared;
10 opp-480000000 {
11 opp-hz = /bits/ 64 <480000000>;
12 opp-microvolt = <900000>;
13 clock-latency-ns = <244144>; /* 8 32k periods */
14 opp-supported-hw = <0x3f>;
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/freebsd/sys/contrib/openzfs/lib/libspl/
H A Datomic.c10 * or https://opensource.org/licenses/CDDL-1.0.
40 ATOMIC_INC(32, uint32_t)
56 ATOMIC_DEC(32, uint32_t)
65 void atomic_add_##name(volatile type1 *target, type2 bits) \
67 (void) __atomic_add_fetch(target, bits, __ATOMIC_SEQ_CST); \
71 atomic_add_ptr(volatile void *target, ssize_t bits)
73 (void) __atomic_add_fetch((void **)target, bits, __ATOMIC_SEQ_CST);
78 ATOMIC_ADD(32, uint32_t, int32_t)
87 void atomic_sub_##name(volatile type1 *target, type2 bits) \ in ATOMIC_ADD()
89 (void) __atomic_sub_fetch(target, bits, __ATOMIC_SEQ_CST); \ in ATOMIC_ADD()
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/freebsd/contrib/gdtoa/
H A Dstrtordd.c36 ULtodd(L, bits, exp, k) ULong *L; ULong *bits; Long exp; int k; in ULtodd() argument
38 ULtodd(ULong *L, ULong *bits, Long exp, int k)
50 L[_1] = (bits[1] >> 21 | bits[2] << 11) & (ULong)0xffffffffL;
51 L[_0] = (bits[2] >> 21) | (bits[3] << 11 & 0xfffff)
54 if (bits[1] &= 0x1fffff) {
55 i = hi0bits(bits[1]) - 11;
57 i = exp - 1;
61 exp -= i;
63 bits[1] = bits[1] << i | bits[0] >> (32-i);
64 bits[0] = bits[0] << i & (ULong)0xffffffffL;
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H A Dstrtopdd.c42 static FPI fpi0 = { 106, 1-1023, 2046-1023-106+1, 1, 1 };
44 static FPI fpi0 = { 106, 1-1023-53+1, 2046-1023-106+1, 1, 0 };
46 ULong bits[4]; local
60 rv = strtodg(s, sp, fpi, &exp, bits);
65 u->d[0] = u->d[1] = 0.;
69 u->L[_1] = (bits[1] >> 21 | bits[2] << 11) & 0xffffffffL;
70 u->L[_0] = (bits[2] >> 21) | ((bits[3] << 11) & 0xfffff)
73 if (bits[1] &= 0x1fffff) {
74 i = hi0bits(bits[1]) - 11;
76 i = exp - 1;
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormatsF2.td1 //===- CSKYInstrFormatsF2.td - CSKY Float2.0 Instr Format --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
20 class F2_XYZ<bits<5> datatype, bits<6> sop, string opcodestr, dag outs, dag ins,
23 bits<5> vry;
24 bits<5> vrx;
25 bits<5> vrz;
27 let Inst{25-21} = vry;
28 let Inst{20-16} = vrx;
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/freebsd/sys/dts/arm64/overlays/
H A Dsun50i-h5-opp.dtso1 /dts-v1/;
4 #include <dt-bindings/clock/sun8i-h3-ccu.h>
7 compatible = "allwinner,sun50i-h5";
12 compatible = "operating-points-v2";
13 opp-shared;
16 opp-hz = /bits/ 64 <408000000>;
17 opp-microvolt = <1000000 1000000 1300000>;
18 clock-latency-ns = <244144>; /* 8 32k periods */
22 opp-hz = /bits/ 64 <648000000>;
23 opp-microvolt = <1040000 1040000 1300000>;
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