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/linux/drivers/net/fddi/skfp/h/
H A Dskfbi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
40 #define B0_RAP 0x0000 /* 8 bit register address port */
41 /* 0x0001 - 0x0003: reserved */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
[all …]
/linux/include/linux/
H A Dmath64.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
17 * @dividend: unsigned 64bit dividend
18 * @divisor: unsigned 32bit divisor
19 * @remainder: pointer to unsigned 32bit remainder
23 * This is commonly provided by 32bit archs to provide an optimized 64bit
33 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
34 * @dividend: signed 64bit dividend
35 * @divisor: signed 32bit divisor
36 * @remainder: pointer to signed 32bit remainder
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/linux/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
[all …]
H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
41 PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dmc13xxx.txt4 - compatible : Should be "fsl,mc13783" or "fsl,mc13892"
7 - fsl,mc13xxx-uses-adc : Indicate the ADC is being used
8 - fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used
9 - fsl,mc13xxx-uses-rtc : Indicate the RTC is being used
10 - fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
12 Sub-nodes:
13 - codec: Contain the Audio Codec node.
14 - adc-port: Contain PMIC SSI port number used for ADC.
15 - dac-port: Contain PMIC SSI port number used for DAC.
16 - leds : Contain the led nodes and initial register values in property
[all …]
/linux/drivers/usb/typec/tipd/
H A Dtps6598x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
18 #define TPS_STATUS_PLUG_PRESENT BIT(0)
19 #define TPS_STATUS_PLUG_UPSIDE_DOWN BIT(4)
21 #define TPS_STATUS_PORTROLE BIT(5)
23 #define TPS_STATUS_DATAROLE BIT(6)
25 #define TPS_STATUS_VCONN BIT(7)
27 #define TPS_STATUS_OVERCURRENT BIT(16)
28 #define TPS_STATUS_GOTO_MIN_ACTIVE BIT(26)
29 #define TPS_STATUS_BIST BIT(27)
30 #define TPS_STATUS_HIGH_VOLTAGE_WARNING BIT(28)
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/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn66xx_regs.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
89 /* 1 register (32-bit) to enable Input queues */
92 /* 1 register (32-bit) to enable Output queues */
95 /* 1 register (32-bit) to determine whether Output queues are in reset. */
98 /* 1 register (32-bit) to determine whether Input queues are in reset. */
103 /* 1 register (32-bit) - instr. size of each input queue. */
106 /* 32 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
109 /* 32 registers for Input Queue Start Addr - SLI_PKT0_INSTR_BADDR */
112 /* 32 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
[all …]
/linux/arch/alpha/kernel/
H A Dsys_sable.c1 // SPDX-License-Identifier: GPL-2.0
9 * Code supporting the Sable, Sable-Gamma, and Lynx systems.
39 /* Note mask bit is true for DISABLED irqs. */
42 void (*update_irq_hw)(unsigned long bit, unsigned long mask);
43 void (*ack_irq_hw)(unsigned long bit);
58 * 0-7 (char at 536)
59 * 8-15 (char at 53a)
60 * 16-23 (char at 53c)
64 * Bit Meaning Kernel IRQ
65 *------------------------------------------
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/linux/drivers/staging/media/ipu3/
H A Dipu3-abi.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include "include/uapi/intel-ipu3.h"
15 #define IMGU_DVS_BLOCK_H 32
31 #define IMGU_ABI_AF_MAX_CELLS_PER_SET 32
32 #define IMGU_ABI_AWB_FR_MAX_CELLS_PER_SET 32
46 #define IMGU_PM_CTRL_START BIT(0)
47 #define IMGU_PM_CTRL_CFG_DONE BIT(1)
48 #define IMGU_PM_CTRL_RACE_TO_HALT BIT(2)
49 #define IMGU_PM_CTRL_NACK_ALL BIT(3)
50 #define IMGU_PM_CTRL_CSS_PWRDN BIT(4)
[all …]
/linux/lib/
H A Diomap_copy.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * __iowrite32_copy - copy data to MMIO space, in 32-bit units
11 * @to: destination, in MMIO space (must be 32-bit aligned)
12 * @from: source (must be 32-bit aligned)
13 * @count: number of 32-bit quantities to copy
15 * Copy data from kernel space to MMIO space, in units of 32 bits at a
33 * __ioread32_copy - copy data from MMIO space, in 32-bit units
34 * @to: destination (must be 32-bit aligned)
35 * @from: source, in MMIO space (must be 32-bit aligned)
36 * @count: number of 32-bit quantities to copy
[all …]
/linux/include/uapi/linux/
H A Dswab.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
71 __u32 h = val >> 32; in __fswab64()
72 __u32 l = val & ((1ULL << 32) - 1); in __fswab64()
73 return (((__u64)__fswab32(l)) << 32) | ((__u64)(__fswab32(h))); in __fswab64()
98 * __swab16 - return a byteswapped 16-bit value
111 * __swab32 - return a byteswapped 32-bit value
124 * __swab64 - return a byteswapped 64-bit value
140 #else /* __BITS_PER_LONG == 32 */ in __swab()
146 * __swahw32 - return a word-swapped 32-bit value
157 * __swahb32 - return a high and low byte-swapped 32-bit value
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/linux/fs/ext4/
H A Dinode-test.c1 // SPDX-License-Identifier: GPL-2.0
28 #define LOWER_MSB_1 (-(UPPER_MSB_0) - 1L) /* avoid overflow */
33 #define UPPER_MSB_1 (-1L)
38 #define MAX_NANOSECONDS ((1L << 30) - 1)
43 "1901-12-13 Lower bound of 32bit < 0 timestamp, no extra bits"
45 "1969-12-31 Upper bound of 32bit < 0 timestamp, no extra bits"
47 "1970-01-01 Lower bound of 32bit >=0 timestamp, no extra bits"
49 "2038-01-19 Upper bound of 32bit >=0 timestamp, no extra bits"
51 "2038-01-19 Lower bound of 32bit <0 timestamp, lo extra sec bit on"
53 "2106-02-07 Upper bound of 32bit <0 timestamp, lo extra sec bit on"
[all …]
/linux/Documentation/staging/
H A Dcrc32.rst5 A CRC is a long-division remainder. You add the CRC to the message,
11 protocols put the end-of-frame flag after the CRC.
15 - We're working in binary, so the digits are only 0 and 1, and
16 - When dividing polynomials, there are no carries. Rather than add and
17 subtract, we just xor. Thus, we tend to get a bit sloppy about
21 To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial.
22 Since it's 33 bits long, bit 32 is always going to be set, so usually the
23 CRC is written in hex with the most significant bit omitted. (If you're
24 familiar with the IEEE 754 floating-point format, it's the same idea.)
28 the best error-detecting properties, this should correspond to the
[all …]
/linux/arch/s390/kernel/
H A Dmodule.c1 // SPDX-License-Identifier: GPL-2.0+
26 #include <asm/nospec-branch.h>
43 execmem_free(mod->arch.trampolines_start); in module_arch_cleanup()
50 mod->state == MODULE_STATE_LIVE) in module_arch_freeing_init()
53 vfree(mod->arch.syminfo); in module_arch_freeing_init()
54 mod->arch.syminfo = NULL; in module_arch_freeing_init()
61 info = me->arch.syminfo + ELF_R_SYM (rela->r_info); in check_rela()
62 switch (ELF_R_TYPE (rela->r_info)) { in check_rela()
63 case R_390_GOT12: /* 12 bit GOT offset. */ in check_rela()
64 case R_390_GOT16: /* 16 bit GOT offset. */ in check_rela()
[all …]
/linux/tools/testing/selftests/powerpc/vphn/
H A Dtest-vphn.c1 // SPDX-License-Identifier: GPL-2.0
41 "vphn: 1 x 16-bit value",
56 "vphn: 2 x 16-bit values",
72 "vphn: 3 x 16-bit values",
89 "vphn: 4 x 16-bi
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/linux/lib/math/
H A Ddiv64.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on former do_div() implementation from asm-parisc/div64.h:
6 * Copyright (C) 1999 Hewlett-Packard Co
7 * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
10 * Generic C version of 64bit/32bit division and modulo, with
11 * 64bit result and 32bit remainder.
13 * The fast case for (n>>32 == 0) is handled inline by do_div().
16 * for some CPUs. __div64_32() can be overridden by linking arch-specific
28 /* Not needed on 64bit architectures */
29 #if BITS_PER_LONG == 32
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/linux/drivers/acpi/acpica/
H A Dtbfadt.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: tbfadt - FADT table utilities
6 * Copyright (C) 2000 - 2025, Intel Corp.
143 * PARAMETERS: generic_address - GAS struct to be initialized
144 * space_id - ACPI Space ID for this register
145 * byte_width - Width of this register
146 * address - Address of the register
147 * register_name - ASCII name of the ACPI register
166 * Bit width field in the GAS is only one byte long, 255 max. in acpi_tb_init_generic_address()
170 if (byte_width > 31) { /* (31*8)=248, (32*8)=256 */ in acpi_tb_init_generic_address()
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/linux/drivers/eisa/
H A Deisa.ids6 # Marc Zyngier <maz@wild-wind.fr.eu.org>
10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter"
11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter"
12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter"
13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter"
14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
25 ACE7010 "ACME Multi-Function Board"
39 ACR1711 "AcerFrame 1000 486/33 SYSTEM-2"
41 ACR3211 "AcerFrame 3000MP 486 SYSTEM-1"
[all …]
/linux/arch/arm64/include/asm/
H A Dkgdb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <asm/debug-monitors.h>
34 * r0-r30: 64 bit
35 * sp,pc : 64 bit
36 * pstate : 32 bit
39 * f0-f31: 128 bit
40 * fpsr & fpcr: 32 bit
41 * Total: 32 + 2
45 * Architecture Reference Manual that claimed "SPSR_ELx is a 32-bit register".
46 * and, as a result, allocated only 32-bits for the PSTATE in the remote
[all …]
/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNQGAMA 64G 3.3V 8-bit",
50 {"SDTNRGAMA 64G 3.3V 8-bit",
53 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
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/linux/arch/mips/include/asm/
H A Dmips-gic.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
29 /* For read-only shared registers */
34 /* For read-write shared registers */
39 /* For read-only local registers */
44 /* For read-write local registers */
49 /* For read-only shared per-interrupt registers */
58 BUILD_BUG_ON(sz != 32); \
62 /* For read-write shared per-interrupt registers */
69 BUILD_BUG_ON(sz != 32); \
[all …]
/linux/drivers/tee/optee/
H A Doptee_smc.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
3 * Copyright (c) 2015-2021, Linaro Limited
8 #include <linux/arm-smccc.h>
28 * Normal cached memory (write-back), shareable for SMP systems and not
36 * 32-bit registers.
44 * 384fb3e0-e7f8-11e3-af63-0002a5d5c51b.
75 * Used by non-secure world to figure out which Trusted OS is installed.
78 * Returns UUID in a0-4 in the same way as OPTEE_SMC_CALLS_UID
88 * Used by non-secure world to figure out which version of the Trusted OS
92 * Returns revision in a0-1 in the same way as OPTEE_SMC_CALLS_REVISION
[all …]
/linux/Documentation/scsi/
H A Daic7xxx.rst1 .. SPDX-License-Identifier: GPL-2.0
5 Adaptec Aic7xxx Fast -> Ultra160 Family Manager Set v7.0
26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
[all …]
/linux/drivers/crypto/intel/qat/qat_common/
H A Dicp_qat_hw.h1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
81 ICP_ACCEL_MASK_CIPHER_SLICE = BIT(0),
82 ICP_ACCEL_MASK_AUTH_SLICE = BIT(1),
83 ICP_ACCEL_MASK_PKE_SLICE = BIT(2),
84 ICP_ACCEL_MASK_COMPRESS_SLICE = BIT(3),
85 ICP_ACCEL_MASK_LZS_SLICE = BIT(4),
86 ICP_ACCEL_MASK_EIA3_SLICE = BIT(5),
87 ICP_ACCEL_MASK_SHA3_SLICE = BIT(6),
91 ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = BIT(0),
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-fau.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
57 * bit will be set. Otherwise the value of the register before
67 * bit will be set. Otherwise the value of the register before
77 * bit will be set. Otherwise the value of the register before
87 * bit will be set. Otherwise the value of the register before
97 * the error bit will be set. Otherwise the value of the
124 * - Step by 2 for 16 bit access.
125 * - Step by 4 for 32 bit access.
[all …]

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