/linux/Documentation/devicetree/bindings/timer/ |
H A D | renesas,cmt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock 26 - items: 27 - enum: 28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1 29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1 [all …]
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/linux/Documentation/arch/arm64/ |
H A D | asymmetric-32bit.rst | 2 Asymmetric 32-bit SoCs 7 This document describes the impact of asymmetric 32-bit SoCs on the 8 execution of 32-bit (``AArch32``) applications. 10 Date: 2021-05-17 16 of the CPUs are capable of executing 32-bit user applications. On such 19 ``execve(2)`` of 32-bit ELF binaries, with the latter returning 20 ``-ENOEXEC``. If the mismatch is detected during late onlining of a 21 64-bit-only CPU, then the onlining operation fails and the new CPU is 25 running legacy 32-bit binaries. Unsurprisingly, that doesn't work very 28 It seems inevitable that future SoCs will drop 32-bit support [all …]
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/linux/drivers/net/fddi/skfp/h/ |
H A D | skfbi.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 15 * FDDI-Fx (x := {I(SA), P(CI)}) 19 /*--------------------------------------------------------------------------*/ 40 #define B0_RAP 0x0000 /* 8 bit register address port */ 41 /* 0x0001 - 0x0003: reserved */ 42 #define B0_CTRL 0x0004 /* 8 bit control register */ 43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */ 44 #define B0_LED 0x0006 /* 8 Bit LED register */ 45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */ 46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */ [all …]
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/linux/include/linux/ |
H A D | math64.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 16 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder 17 * @dividend: unsigned 64bit dividend 18 * @divisor: unsigned 32bit divisor 19 * @remainder: pointer to unsigned 32bit remainder 23 * This is commonly provided by 32bit archs to provide an optimized 64bit 33 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder 34 * @dividend: signed 64bit dividend 35 * @divisor: signed 32bit divisor 36 * @remainder: pointer to signed 32bit remainder [all …]
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H A D | nfs4.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 108 OP_SAVEFH = 32, 327 NF4BLK = 3, /* Special File - block device */ 328 NF4CHR = 4, /* Special File - character device */ 330 NF4SOCK = 6, /* Special File - socket */ 331 NF4FIFO = 7, /* Special File - fifo */ 434 FATTR4_MIMETYPE = 32, 523 * attribute bits within 32-bit word boundaries. 527 #define FATTR4_WORD0_SUPPORTED_ATTRS BIT(FATTR4_SUPPORTED_ATTRS) 528 #define FATTR4_WORD0_TYPE BIT(FATTR4_TYPE) [all …]
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/linux/arch/s390/include/asm/ |
H A D | elf.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 5 * Derived from "include/asm-i386/elf.h" 13 #define R_390_8 1 /* Direct 8 bit. */ 14 #define R_390_12 2 /* Direct 12 bit. */ 15 #define R_390_16 3 /* Direct 16 bit. */ 16 #define R_390_32 4 /* Direct 32 bit. */ 17 #define R_390_PC32 5 /* PC relative 32 bit. */ 18 #define R_390_GOT12 6 /* 12 bit GOT offset. */ 19 #define R_390_GOT32 7 /* 32 bit GOT offset. */ 20 #define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ [all …]
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/linux/drivers/net/ethernet/marvell/ |
H A D | skge.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 131 /* B0_CTST 16 bit Control/Status register */ 133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */ 134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */ 135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */ 138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */ 142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */ 148 /* B0_LED 8 Bit LED register */ 149 /* Bit 7.. 2: reserved */ 153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ [all …]
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H A D | sky2.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 30 /* Yukon-2 */ 32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */ 33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */ 34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */ 35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */ 36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */ 37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */ 38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */ 41 PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */ [all …]
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/linux/Documentation/devicetree/bindings/mfd/ |
H A D | mc13xxx.txt | 4 - compatible : Should be "fsl,mc13783" or "fsl,mc13892" 7 - fsl,mc13xxx-uses-adc : Indicate the ADC is being used 8 - fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used 9 - fsl,mc13xxx-uses-rtc : Indicate the RTC is being used 10 - fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used 12 Sub-nodes: 13 - codec: Contain the Audio Codec node. 14 - adc-port: Contain PMIC SSI port number used for ADC. 15 - dac-port: Contain PMIC SSI port number used for DAC. 16 - leds : Contain the led nodes and initial register values in property [all …]
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/linux/drivers/net/ethernet/cavium/liquidio/ |
H A D | cn66xx_regs.h | 7 * Copyright (c) 2003-2016 Cavium, Inc. 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 89 /* 1 register (32-bit) to enable Input queues */ 92 /* 1 register (32-bit) to enable Output queues */ 95 /* 1 register (32-bit) to determine whether Output queues are in reset. */ 98 /* 1 register (32-bit) to determine whether Input queues are in reset. */ 103 /* 1 register (32-bit) - instr. size of each input queue. */ 106 /* 32 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */ 109 /* 32 registers for Input Queue Start Addr - SLI_PKT0_INSTR_BADDR */ 112 /* 32 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */ [all …]
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/linux/arch/alpha/kernel/ |
H A D | sys_sable.c | 1 // SPDX-License-Identifier: GPL-2.0 9 * Code supporting the Sable, Sable-Gamma, and Lynx systems. 39 /* Note mask bit is true for DISABLED irqs. */ 42 void (*update_irq_hw)(unsigned long bit, unsigned long mask); 43 void (*ack_irq_hw)(unsigned long bit); 58 * 0-7 (char at 536) 59 * 8-15 (char at 53a) 60 * 16-23 (char at 53c) 64 * Bit Meaning Kernel IRQ 65 *------------------------------------------ [all …]
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/linux/drivers/staging/media/ipu3/ |
H A D | ipu3-abi.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 7 #include "include/uapi/intel-ipu3.h" 15 #define IMGU_DVS_BLOCK_H 32 31 #define IMGU_ABI_AF_MAX_CELLS_PER_SET 32 32 #define IMGU_ABI_AWB_FR_MAX_CELLS_PER_SET 32 46 #define IMGU_PM_CTRL_START BIT(0) 47 #define IMGU_PM_CTRL_CFG_DONE BIT(1) 48 #define IMGU_PM_CTRL_RACE_TO_HALT BIT(2) 49 #define IMGU_PM_CTRL_NACK_ALL BIT(3) 50 #define IMGU_PM_CTRL_CSS_PWRDN BIT(4) [all …]
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/linux/lib/ |
H A D | iomap_copy.c | 1 // SPDX-License-Identifier: GPL-2.0-only 10 * __iowrite32_copy - copy data to MMIO space, in 32-bit units 11 * @to: destination, in MMIO space (must be 32-bit aligned) 12 * @from: source (must be 32-bit aligned) 13 * @count: number of 32-bit quantities to copy 15 * Copy data from kernel space to MMIO space, in units of 32 bits at a 33 * __ioread32_copy - copy data from MMIO space, in 32-bit units 34 * @to: destination (must be 32-bit aligned) 35 * @from: source, in MMIO space (must be 32-bit aligned) 36 * @count: number of 32-bit quantities to copy [all …]
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/linux/include/uapi/linux/ |
H A D | swab.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 71 __u32 h = val >> 32; in __fswab64() 72 __u32 l = val & ((1ULL << 32) - 1); in __fswab64() 73 return (((__u64)__fswab32(l)) << 32) | ((__u64)(__fswab32(h))); in __fswab64() 98 * __swab16 - return a byteswapped 16-bit value 111 * __swab32 - return a byteswapped 32-bit value 124 * __swab64 - return a byteswapped 64-bit value 140 #else /* __BITS_PER_LONG == 32 */ in __swab() 146 * __swahw32 - return a word-swapped 32-bit value 157 * __swahb32 - return a high and low byte-swapped 32-bit value [all …]
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/linux/fs/ext4/ |
H A D | inode-test.c | 1 // SPDX-License-Identifier: GPL-2.0 28 #define LOWER_MSB_1 (-(UPPER_MSB_0) - 1L) /* avoid overflow */ 33 #define UPPER_MSB_1 (-1L) 38 #define MAX_NANOSECONDS ((1L << 30) - 1) 43 "1901-12-13 Lower bound of 32bit < 0 timestamp, no extra bits" 45 "1969-12-31 Upper bound of 32bit < 0 timestamp, no extra bits" 47 "1970-01-01 Lower bound of 32bit >=0 timestamp, no extra bits" 49 "2038-01-19 Upper bound of 32bit >=0 timestamp, no extra bits" 51 "2038-01-19 Lower bound of 32bit <0 timestamp, lo extra sec bit on" 53 "2106-02-07 Upper bound of 32bit <0 timestamp, lo extra sec bit on" [all …]
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/linux/Documentation/admin-guide/ |
H A D | highuid.rst | 2 Notes on the change from 16-bit UIDs to 32-bit UIDs 8 - kernel code MUST take into account __kernel_uid_t and __kernel_uid32_t 12 - kernel code should use uid_t and gid_t in kernel-private structures and 15 What's left to be done for 32-bit UIDs on all Linux architectures: 17 - Disk quotas have an interesting limitation that is not related to the 22 properly with huge UIDs. If it can deal with 64-bit file offsets on all 25 - Decide whether or not to keep backwards compatibility with the system 27 (currently, the old 16-bit UID and GID are still written to disk, and 28 part of the former pad space is used to store separate 32-bit UID and 31 - Need to validate that OS emulation calls the 16-bit UID [all …]
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/linux/Documentation/staging/ |
H A D | crc32.rst | 5 A CRC is a long-division remainder. You add the CRC to the message, 11 protocols put the end-of-frame flag after the CRC. 15 - We're working in binary, so the digits are only 0 and 1, and 16 - When dividing polynomials, there are no carries. Rather than add and 17 subtract, we just xor. Thus, we tend to get a bit sloppy about 21 To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial. 22 Since it's 33 bits long, bit 32 is always going to be set, so usually the 23 CRC is written in hex with the most significant bit omitted. (If you're 24 familiar with the IEEE 754 floating-point format, it's the same idea.) 28 the best error-detecting properties, this should correspond to the [all …]
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/linux/arch/s390/kernel/ |
H A D | module.c | 1 // SPDX-License-Identifier: GPL-2.0+ 26 #include <asm/nospec-branch.h> 43 execmem_free(mod->arch.trampolines_start); in module_arch_cleanup() 50 mod->state == MODULE_STATE_LIVE) in module_arch_freeing_init() 53 vfree(mod->arch.syminfo); in module_arch_freeing_init() 54 mod->arch.syminfo = NULL; in module_arch_freeing_init() 61 info = me->arch.syminfo + ELF_R_SYM (rela->r_info); in check_rela() 62 switch (ELF_R_TYPE (rela->r_info)) { in check_rela() 63 case R_390_GOT12: /* 12 bit GOT offset. */ in check_rela() 64 case R_390_GOT16: /* 16 bit GOT offset. */ in check_rela() [all …]
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/linux/tools/testing/selftests/powerpc/vphn/ |
H A D | test-vphn.c | 1 // SPDX-License-Identifier: GPL-2.0 41 "vphn: 1 x 16-bit value", 56 "vphn: 2 x 16-bit values", 72 "vphn: 3 x 16-bit values", 89 "vphn: 4 x 16-bit values", 107 /* Parsing the next 16-bit value out of the next 64-bit input 110 "vphn: 5 x 16-bit values", 129 /* Parse at most 6 x 64-bit input values */ 130 "vphn: 24 x 16-bit values", 168 "vphn: 1 x 32-bit value", [all …]
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/linux/lib/math/ |
H A D | div64.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Based on former do_div() implementation from asm-parisc/div64.h: 6 * Copyright (C) 1999 Hewlett-Packard Co 7 * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com> 10 * Generic C version of 64bit/32bit division and modulo, with 11 * 64bit result and 32bit remainder. 13 * The fast case for (n>>32 == 0) is handled inline by do_div(). 16 * for some CPUs. __div64_32() can be overridden by linking arch-specific 28 /* Not needed on 64bit architectures */ 29 #if BITS_PER_LONG == 32 [all …]
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/linux/drivers/gpu/drm/i915/gvt/ |
H A D | fb_decoder.c | 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 56 {DRM_FORMAT_C8, 8, "8-bit Indexed"}, 57 {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"}, 58 {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"}, 59 {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"}, 61 {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"}, 62 {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"}, 64 /* non-supported format has bpp default to 0 */ 69 {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"}, 70 {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"}, [all …]
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/linux/drivers/acpi/acpica/ |
H A D | tbfadt.c | 1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 4 * Module Name: tbfadt - FADT table utilities 6 * Copyright (C) 2000 - 2023, Intel Corp. 143 * PARAMETERS: generic_address - GAS struct to be initialized 144 * space_id - ACPI Space ID for this register 145 * byte_width - Width of this register 146 * address - Address of the register 147 * register_name - ASCII name of the ACPI register 166 * Bit width field in the GAS is only one byte long, 255 max. in acpi_tb_init_generic_address() 170 if (byte_width > 31) { /* (31*8)=248, (32*8)=256 */ in acpi_tb_init_generic_address() [all …]
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/linux/arch/arm64/include/asm/ |
H A D | kgdb.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 15 #include <asm/debug-monitors.h> 34 * r0-r30: 64 bit 35 * sp,pc : 64 bit 36 * pstate : 32 bit 39 * f0-f31: 128 bit 40 * fpsr & fpcr: 32 bit 41 * Total: 32 + 2 45 * Architecture Reference Manual that claimed "SPSR_ELx is a 32-bit register". 46 * and, as a result, allocated only 32-bits for the PSTATE in the remote [all …]
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/linux/drivers/eisa/ |
H A D | eisa.ids | 6 # Marc Zyngier <maz@wild-wind.fr.eu.org> 10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter" 11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter" 12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter" 13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter" 14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter" 15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter" 25 ACE7010 "ACME Multi-Function Board" 39 ACR1711 "AcerFrame 1000 486/33 SYSTEM-2" 41 ACR3211 "AcerFrame 3000MP 486 SYSTEM-1" [all …]
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/linux/drivers/mtd/nand/raw/ |
H A D | nand_ids.c | 1 // SPDX-License-Identifier: GPL-2.0-only 29 {"TC58NVG0S3E 1G 3.3V 8-bit", 32 {"TC58NVG2S0F 4G 3.3V 8-bit", 35 {"TC58NVG2S0H 4G 3.3V 8-bit", 38 {"TC58NVG3S0F 8G 3.3V 8-bit", 41 {"TC58NVG5D2 32G 3.3V 8-bit", 44 {"TC58NVG6D2 64G 3.3V 8-bit", 47 {"SDTNQGAMA 64G 3.3V 8-bit", 50 {"SDTNRGAMA 64G 3.3V 8-bit", 53 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit", [all …]
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