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/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DMSP430Target.def1 //===--- MSP430Target.def - MSP430 Feature/Processor Database----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 // Target/MSP430/gen-msp430-def.py - use this tool rather than adding
15 //===----------------------------------------------------------------------===//
203 // With 16-bit hardware multiplier
204 MSP430_MCU_FEAT("msp430c336", "16bit")
205 MSP430_MCU_FEAT("msp430c337", "16bit")
206 MSP430_MCU_FEAT("msp430cg4616", "16bit")
207 MSP430_MCU_FEAT("msp430cg4617", "16bit")
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/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Drenesas,cmt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
26 - items:
27 - enum:
28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dmmintrin.h1 /*===---- mmintrin.h - MMX intrinsics --------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
26 __attribute__((__always_inline__, __nodebug__, __target__("mmx,no-evex512"), \
37 __target__("mmx,no-evex512")))
42 /// Constructs a 64-bit integer vector, setting the lower 32 bits to the
43 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
50 /// A 32-bit integer value.
51 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
52 /// parameter. The upper 32 bits are set to 0.
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H A Dia32intrin.h1 /* ===-------- ia32intrin.h ---------------------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
29 /// Finds the first set bit starting from the least significant bit. The result
38 /// A 32-bit integer operand.
39 /// \returns A 32-bit integer containing the bit number.
46 /// Finds the first set bit starting from the most significant bit. The result
55 /// A 32-bit integer operand.
56 /// \returns A 32-bit integer containing the bit number.
60 return 31 - __builtin_clz((unsigned int)__A); in __bsrd()
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H A Dxmmintrin.h1 /*===---- xmmintrin.h - SSE intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
36 __attribute__((__always_inline__, __nodebug__, __target__("sse,no-evex512"), \
40 __target__("mmx,sse,no-evex512"), __min_vector_width__(64)))
42 /// Adds the 32-bit float values in the low-order bits of the operands.
49 /// A 128-bit vector of [4 x float] containing one of the source operands.
50 /// The lower 32 bits of this operand are used in the calculation.
52 /// A 128-bit vector of [4 x float] containing one of the source operands.
53 /// The lower 32 bits of this operand are used in the calculation.
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H A Dbmi2intrin.h1 /*===---- bmi2intrin.h - BMI2 intrinsics -----------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
20 /// Copies the unsigned 32-bit integer \a __X and zeroes the upper bits
21 /// starting at bit number \a __Y.
26 /// IF i < 32
36 /// The 32-bit source value to copy.
38 /// The lower 8 bits specify the bit number of the lowest bit to zero.
39 /// \returns The partially zeroed 32-bit value.
46 /// Deposit (scatter) low-order bits from the unsigned 32-bit integer \a __X
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H A Dlwpintrin.h1 /*===---- lwpintrin.h - LWP intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
60 /// A 32-bit value is zero-extended and inserted into the 64-bit Data2 field.
62 /// A 32-bit value is inserted into the 32-bit Data1 field.
64 /// A 32-bit immediate value is inserted into the 32-bit Flags field.
82 /// A 32-bit value is zero-extended and inserted into the 64-bit Data2 field.
84 /// A 32-bit value is inserted into the 32-bit Data1 field.
86 /// A 32-bit immediate value is inserted into the 32-bit Flags field.
101 /// A 64-bit value is inserted into the 64-bit Data2 field.
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H A Davxvnniint8intrin.h1 /*===-------- avxvnniint8intrin.h - AVXVNNIINT8 intrinsics -----------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
25 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in \a __A with
26 /// corresponding signed 8-bit integers in \a __B, producing 4 intermediate
27 /// signed 16-bit results. Sum these 4 results with the corresponding
28 /// 32-bit integer in \a __W, and store the packed 32-bit results in \a dst.
39 /// A 128-bit vector of [16 x char].
41 /// A 128-bit vector of [16 x char].
43 /// A 128-bit vector of [4 x int].
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H A Dfmaintrin.h1 /*===---- fmaintrin.h - FMA intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
21 /// Computes a multiply-add of 128-bit vectors of [4 x float].
29 /// A 128-bit vector of [4 x float] containing the multiplicand.
31 /// A 128-bit vector of [4 x float] containing the multiplier.
33 /// A 128-bit vector of [4 x float] containing the addend.
34 /// \returns A 128-bit vector of [4 x float] containing the result.
41 /// Computes a multiply-add of 128-bit vectors of [2 x double].
49 /// A 128-bit vector of [2 x double] containing the multiplicand.
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H A Davxneconvertintrin.h1 /*===-------------- avxneconvertintrin.h - AVXNECONVERT --------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
28 /// Convert scalar BF16 (16-bit) floating-point element
30 /// single-precision (32-bit) floating-point, broadcast it to packed
31 /// single-precision (32-bit) floating-point elements, and store the results in
43 /// A pointer to a 16-bit memory location. The address of the memory
46 /// A 128-bit vector of [4 x float].
51 /// m := j*32
61 /// Convert scalar BF16 (16-bit) floating-point element
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H A Draointintrin.h1 /*===----------------------- raointintrin.h - RAOINT ------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
20 /// Atomically add a 32-bit value at memory operand \a __A and a 32-bit \a __B,
31 /// A pointer to a 32-bit memory location.
33 /// A 32-bit integer value.
42 /// Atomically and a 32-bit value at memory operand \a __A and a 32-bit \a __B,
53 /// A pointer to a 32-bit memory location.
55 /// A 32-bit integer value.
64 /// Atomically or a 32-bit value at memory operand \a __A and a 32-bit \a __B,
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H A Davxvnniint16intrin.h1 /*===----------- avxvnniint16intrin.h - AVXVNNIINT16 intrinsics-------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
26 /// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
27 /// corresponding unsigned 16-bit integers in \a __B, producing 2 intermediate
28 /// signed 16-bit results. Sum these 2 results with the corresponding
29 /// 32-bit integer in \a __W, and store the packed 32-bit results in \a dst.
40 /// A 128-bit vector of [4 x int].
42 /// A 128-bit vector of [8 x short].
44 /// A 128-bit vector of [8 x unsigned short].
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H A Davxvnniintrin.h1 /*===--------------- avxvnniintrin.h - VNNI intrinsics --------------------===
22 *===-----------------------------------------------------------------------===
46 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a __A with
47 /// corresponding signed 8-bit integers in \a __B, producing 4 intermediate signed
48 /// 16-bit results. Sum these 4 results with the corresponding 32-bit integer
49 /// in \a __S, and store the packed 32-bit results in DST.
69 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a __A with
70 /// corresponding signed 8-bit integers in \a __B, producing 4 intermediate signed
71 /// 16-bit results. Sum these 4 results with the corresponding 32-bit integer
72 /// in \a __S using signed saturation, and store the packed 32-bit results in DST.
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H A Df16cintrin.h1 /*===---- f16cintrin.h - F16C intrinsics -----------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
23 /* NOTE: Intel documents the 128-bit versions of these as being in emmintrin.h,
28 /// Converts a 16-bit half-precision float value into a 32-bit float
36 /// A 16-bit half-precision float value.
37 /// \returns The converted 32-bit float value.
46 /// Converts a 32-bit single-precision float value to a 16-bit
47 /// half-precision float value.
58 /// A 32-bit single-precision float value to be converted to a 16-bit
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H A Damxintrin.h1 /*===--------------- amxintrin.h - AMX intrinsics -*- C/C++ -*---------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===------------------------------------------------------------------------===
20 __attribute__((__always_inline__, __nodebug__, __target__("amx-tile")))
22 __attribute__((__always_inline__, __nodebug__, __target__("amx-int8")))
24 __attribute__((__always_inline__, __nodebug__, __target__("amx-bf16")))
26 __attribute__((__always_inline__, __nodebug__, __target__("amx-fp16")))
28 /// Load tile configuration from a 64-byte memory location specified by
40 /// A pointer to 512-bits configuration
46 /// Stores the current tile configuration to a 64-byte memory location
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/freebsd/sys/dev/msk/
H A Dif_mskreg.h17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
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/freebsd/sys/contrib/edk2/Include/Library/
H A DBaseLib.h3 functions, file path functions, and CPU architecture-specific functions.
5 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
6 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
18 // Definitions for architecture-specific types
22 /// The IA-32 architecture context buffer used by SetJump() and LongJump().
54 UINT8 XmmBuffer[160]; ///< XMM6-XMM15.
132 /// The RISC-V architecture context buffer used by SetJump() and LongJump().
161 Returns the length of a Null-terminated Unicode string.
165 If String is not aligned on a 16-bit boundary, then ASSERT().
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmc13xxx.txt4 - compatible : Should be "fsl,mc13783" or "fsl,mc13892"
7 - fsl,mc13xxx-uses-adc : Indicate the ADC is being used
8 - fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used
9 - fsl,mc13xxx-uses-rtc : Indicate the RTC is being used
10 - fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
12 Sub-nodes:
13 - codec: Contain the Audio Codec node.
14 - adc-port: Contain PMIC SSI port number used for ADC.
15 - dac-port: Contain PMIC SSI port number used for DAC.
16 - leds : Contain the led nodes and initial register values in property
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/freebsd/sys/contrib/openzfs/config/
H A Dhost-cpu-c-abi.m41 # host-cpu-c-abi.m4 serial 11
2 dnl Copyright (C) 2002-2019 Free Software Foundation, Inc.
24 dnl contains 32-bit instructions, whereas 'sparc64' code contains 64-bit
25 dnl instructions. A process on a SPARC CPU can be in 32-bit mode or in 64-bit
36 dnl - 'arm': test __ARMEL__.
37 dnl - 'mips', 'mipsn32', 'mips64': test _MIPSEB vs. _MIPSEL.
38 dnl - 'powerpc64': test _BIG_ENDIAN vs. _LITTLE_ENDIAN.
41 dnl - Instructions that do not exist on all of these CPUs (cmpxchg,
45 dnl - Speed of execution of the common instruction set is reasonable across
66 # - 64-bit instruction set, 64-bit pointers, 64-bit 'long': x86_64.
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td1 //===-- RISCVSchedule.td - RISC-V Scheduling Definitions ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
12 def WriteShiftImm : SchedWrite; // 32 or 64-bit shift by immediate operations
13 def WriteShiftImm32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
14 def WriteShiftReg : SchedWrite; // 32 or 64-bit shift by immediate operations
15 def WriteShiftReg32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
16 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide
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/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DInstructionUtils.h1 //===-- InstructionUtils.h --------------------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
15 // Common utilities for manipulating instruction bit fields.
19 // Return the bit field(s) from the most significant bit (msbit) to the
20 // least significant bit (lsbit) of a 64-bit unsigned value.
24 return (bits >> lsbit) & ((1ull << (msbit - lsbit + 1)) - 1); in Bits64()
27 // Return the bit field(s) from the most significant bit (msbit) to the
28 // least significant bit (lsbit) of a 32-bit unsigned value.
31 assert(msbit < 32 && lsbit <= msbit); in Bits32()
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/freebsd/sys/dev/sfxge/common/
H A Defx_regs_pci.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
41 * PC_VEND_ID_REG(16bit):
52 * PC_DEV_ID_REG(16bit):
63 * PC_CMD_REG(16bit):
94 * PC_STAT_REG(16bit):
125 * PC_REV_ID_REG(8bit):
136 * PC_CC_REG(24bit):
151 * PC_CACHE_LSIZE_REG(8bit):
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H A Defx_regs.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
48 * FR_AB_EE_VPD_CFG0_REG_SF(128bit):
54 * FR_AB_EE_VPD_CFG0_REG(128bit):
76 #define FRF_AB_EE_VPD_BASE_LBN 32
94 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit):
100 * FR_AB_PCIE_SD_CTL0123_REG(128bit):
130 #define FRF_AB_PCIE_PARLPBK_LBN 32
162 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit):
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64GenRegisterBankInfo.def1 //===- AArch64GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
19 {0, 32, AArch64::FPRRegBank},
20 // 2: FPR 64-bit value.
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEFixupKinds.h1 //===-- VEFixupKinds.h - VE Specific Fixup Entries --------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
17 /// fixup_ve_reflong - 32-bit fixup corresponding to foo
20 /// fixup_ve_srel32 - 32-bit fixup corresponding to foo for relative branch
23 /// fixup_ve_hi32 - 32-bit fixup corresponding to foo\@hi
26 /// fixup_ve_lo32 - 32-bit fixup corresponding to foo\@lo
29 /// fixup_ve_pc_hi32 - 32-bit fixup corresponding to foo\@pc_hi
32 /// fixup_ve_pc_lo32 - 32-bit fixup corresponding to foo\@pc_lo
35 /// fixup_ve_got_hi32 - 32-bit fixup corresponding to foo\@got_hi
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