Lines Matching +full:32 +full:- +full:bit

1 # host-cpu-c-abi.m4 serial 11
2 dnl Copyright (C) 2002-2019 Free Software Foundation, Inc.
24 dnl contains 32-bit instructions, whereas 'sparc64' code contains 64-bit
25 dnl instructions. A process on a SPARC CPU can be in 32-bit mode or in 64-bit
36 dnl - 'arm': test __ARMEL__.
37 dnl - 'mips', 'mipsn32', 'mips64': test _MIPSEB vs. _MIPSEL.
38 dnl - 'powerpc64': test _BIG_ENDIAN vs. _LITTLE_ENDIAN.
41 dnl - Instructions that do not exist on all of these CPUs (cmpxchg,
45 dnl - Speed of execution of the common instruction set is reasonable across
66 # - 64-bit instruction set, 64-bit pointers, 64-bit 'long': x86_64.
67 # - 64-bit instruction set, 64-bit pointers, 32-bit 'long': x86_64
69 # - 64-bit instruction set, 32-bit pointers, 32-bit 'long': x86_64-x32.
70 # - 32-bit instruction set, 32-bit pointers, 32-bit 'long': i386.
88 [gl_cv_host_cpu_c_abi=x86_64-x32],
94 alphaev[4-8] | alphaev56 | alphapca5[67] | alphaev6[78] )
103 # - aarch64 instruction set, 64-bit pointers, 64-bit 'long': arm64.
104 # - aarch64 instruction set, 32-bit pointers, 32-bit 'long': arm64-ilp32.
105 # - 32-bit instruction set, 32-bit pointers, 32-bit 'long': arm or armhf.
122 [gl_cv_host_cpu_c_abi=arm64-ilp32],
124 [# Don't distinguish little-endian and big-endian arm, since they
128 # But distinguish arm which passes floating-point arguments and
129 # return values in integer registers (r0, r1, ...) - this is
130 # gcc -mfloat-abi=soft or gcc -mfloat-abi=softfp - from arm which
132 # (d0, d1, ...) - this is gcc -mfloat-abi=hard. GCC 4.6 or newer
137 AC_TRY_COMMAND(${CC-cc} $CFLAGS $CPPFLAGS $gl_c_asm_opt conftest.c) >/dev/null 2>&1
143 rm -f conftest*
148 # On hppa, the C compiler may be generating 32-bit code or 64-bit
163 # On ia64 on HP-UX, the C compiler may be generating 64-bit code or
164 # 32-bit code. In the latter case, it defines _ILP32.
173 [gl_cv_host_cpu_c_abi=ia64-ilp32],
179 # at 32.
191 # In the 32 ABI, _ABIO32 is defined, _ABIN32 is not defined (but
210 # 32-bit code. And on powerpc-ibm-aix systems, the C compiler may
211 # be generating 64-bit code.
230 [gl_cv_host_cpu_c_abi=powerpc64-elfv2],
266 # 'float' and 'double' are passed in floating-point registers.
268 # 'float' are passed in floating-point registers.
270 # No values are passed in floating-point registers.
291 gl_cv_host_cpu_c_abi="${cpu}-${main_abi}${float_abi}"
295 # On s390x, the C compiler may be generating 64-bit (= s390x) code
296 # or 31-bit (= s390) code.
310 # UltraSPARCs running Linux have `uname -m` = "sparc64", but the
311 # C compiler still generates 32-bit code.
331 HOST_CPU=`echo "$gl_cv_host_cpu_c_abi" | sed -e 's/-.*//'`
340 sed -e 's/-/_/g' >> confdefs.h <<EOF
460 dnl (application binary interface) is a 32-bit one, or to 'no' otherwise.
465 AC_CACHE_CHECK([32-bit host C ABI], [gl_cv_host_cpu_c_abi_32bit],
466 [if test -n "$gl_cv_host_cpu_c_abi"; then
468 …i386 | x86_64-x32 | arm | armhf | arm64-ilp32 | hppa | ia64-ilp32 | mips | mipsn32 | powerpc | ris…
485 # - 64-bit instruction set, 64-bit pointers, 64-bit 'long': x86_64.
486 # - 64-bit instruction set, 64-bit pointers, 32-bit 'long': x86_64
488 # - 64-bit instruction set, 32-bit pointers, 32-bit 'long': x86_64-x32.
489 # - 32-bit instruction set, 32-bit pointers, 32-bit 'long': i386.
508 # - aarch64 instruction set, 64-bit pointers, 64-bit 'long': arm64.
509 # - aarch64 instruction set, 32-bit pointers, 32-bit 'long': arm64-ilp32.
510 # - 32-bit instruction set, 32-bit pointers, 32-bit 'long': arm or armhf.
524 # On hppa, the C compiler may be generating 32-bit code or 64-bit
539 # On ia64 on HP-UX, the C compiler may be generating 64-bit code or
540 # 32-bit code. In the latter case, it defines _ILP32.
555 # at 32.
573 # 32-bit code. And on powerpc-ibm-aix systems, the C compiler may
574 # be generating 64-bit code.
607 # On s390x, the C compiler may be generating 64-bit (= s390x) code
608 # or 31-bit (= s390) code.
622 # UltraSPARCs running Linux have `uname -m` = "sparc64", but the
623 # C compiler still generates 32-bit code.