Home
last modified time | relevance | path

Searched full:31 (Results 1 – 25 of 4168) sorted by relevance

12345678910>>...167

/linux/drivers/media/platform/ti/omap3isp/
H A Dnoise_filter_table.h16 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31,
17 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31
/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl502d.h30 …_WAIT_FOR_IDLE_V 31:0
33 …_SET_DST_CONTEXT_DMA_HANDLE 31:0
36 …_SET_SRC_CONTEXT_DMA_HANDLE 31:0
39 …_SET_SEMAPHORE_CONTEXT_DMA_HANDLE 31:0
78 …_SET_DST_PITCH_V 31:0
81 …_SET_DST_WIDTH_V 31:0
84 …_SET_DST_HEIGHT_V 31:0
90 …_SET_DST_OFFSET_LOWER_V 31:0
130 …_SET_SRC_PITCH_V 31:0
133 …_SET_SRC_WIDTH_V 31:0
[all …]
H A Dcl902d.h31 …_WAIT_FOR_IDLE_V 31:0
82 …_SET_DST_PITCH_V 31:0
85 …_SET_DST_WIDTH_V 31:0
88 …_SET_DST_HEIGHT_V 31:0
94 …_SET_DST_OFFSET_LOWER_V 31:0
146 …_SET_SRC_PITCH_V 31:0
149 …_SET_SRC_WIDTH_V 31:0
152 …_SET_SRC_HEIGHT_V 31:0
158 …_SET_SRC_OFFSET_LOWER_V 31:0
224 …_SET_RENDER_SOLID_PRIM_COLOR_V 31:0
[all …]
H A Dcl5039.h30 …_NO_OPERATION_V 31:0
33 …_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0
36 …_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0
39 …_SET_CONTEXT_DMA_BUFFER_OUT_HANDLE 31:0
65 …_SET_SRC_WIDTH_V 31:0
68 …_SET_SRC_HEIGHT_V 31:0
71 …_SET_SRC_DEPTH_V 31:0
74 …_SET_SRC_LAYER_V 31:0
78 …_SET_SRC_ORIGIN_Y 31:16
104 …_SET_DST_WIDTH_V 31:0
[all …]
/linux/arch/powerpc/lib/
H A Dfeature-fixups-test.S48 or 31,31,31
52 or 31,31,31
68 or 31,31,31
69 or 31,31,31
83 or 31,31,31
84 or 31,31,31
98 or 31,31,31
99 or 31,31,31
302 or 31,31,31; \
303 or 31,31,31; \
[all …]
/linux/arch/powerpc/xmon/
H A Dppc-opc.c1018 else if (value >= 24 && value <= 31) in insert_rx()
1047 else if (value >= 24 && value <= 31) in insert_ry()
1589 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) in insert_mbe()
1630 ret |= 1L << (31 - i); in extract_mbe()
1638 ret &= ~(1L << (31 - i)); in extract_mbe()
3159 {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3161 {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3688 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3748 {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4593 {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
[all …]
/linux/tools/arch/x86/kcpuid/
H A Dcpuid.csv15 0x0, 0, eax, 31:0, max_std_leaf , Highest standard CPUID leaf supported
16 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3
17 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11
18 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7
32 0x1, 0, ebx, 31:24, local_apic_id , Initial local APIC physical ID
63 0x1, 0, ecx, 31, guest_status , System is running as guest; (para-)virtualized system
93 0x1, 0, edx, 31, pbe , Pending Break Enable
102 0x2, 0, eax, 31, eax_invalid , Descriptors 1-3 are invalid if set
107 0x2, 0, ebx, 31, ebx_invalid , Descriptors 4-7 are invalid if set
112 0x2, 0, ecx, 31, ecx_invali
[all...]
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_ethtool.c95 .start = 31,
265 .start = 31,
272 .start = 31,
279 .start = 31,
286 .start = 31,
293 .start = 31,
300 .start = 31,
307 .start = 31,
314 .start = 31,
321 .start = 31,
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h46 #define MT_TX_FREE_PAIR BIT(31)
50 #define MT_TXD0_Q_IDX GENMASK(31, 25)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
67 #define MT_TXD2_FIX_RATE BIT(31)
83 #define MT_TXD3_SN_VALID BIT(31)
97 #define MT_TXD4_PN_LOW GENMASK(31, 0)
99 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
107 #define MT_TXD6_TX_IBF BIT(31)
119 #define MT_TXD7_TXD_LEN GENMASK(31, 30)
141 #define MT_TXS0_FIXED_RATE BIT(31)
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-vsp1-hgo.rst51 - [31:24]
71 - :cspan:`4` R/Cr/H sum [31:0]
73 - :cspan:`4` G/Y/S sum [31:0]
75 - :cspan:`4` B/Cb/V sum [31:0]
77 - :cspan:`4` R/Cr/H bin 0 [31:0]
81 - :cspan:`4` R/Cr/H bin 63 [31:0]
83 - :cspan:`4` G/Y/S bin 0 [31:0]
87 - :cspan:`4` G/Y/S bin 63 [31:0]
89 - :cspan:`4` B/Cb/V bin 0 [31:0]
93 - :cspan:`4` B/Cb/V bin 63 [31:0]
[all …]
/linux/drivers/video/fbdev/nvidia/
H A Dnv_dma.h58 #define SURFACE_PITCH_DST 31:16
75 #define CLIP_POINT_Y 31:16
78 #define CLIP_SIZE_HEIGHT 31:16
89 #define LINE_LINES_POINT0_Y 31:16
95 #define BLIT_POINT_SRC_Y 31:16
98 #define BLIT_POINT_DST_Y 31:16
101 #define BLIT_SIZE_HEIGHT 31:16
112 #define RECT_SOLID_RECTS_X 31:16
118 #define RECT_EXPAND_ONE_COLOR_CLIP_POINT0_Y 31:16
124 #define RECT_EXPAND_ONE_COLOR_SIZE_HEIGHT 31:16
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-ciu2-defs.h31 #define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31)…
32 #define CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31)…
33 …EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull)
34 …N_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull)
35 …N_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull)
36 …X_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull)
37 …X_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull)
38 …X_IP3_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull)
39 …X_IP3_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull)
41 …W_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull)
[all …]
/linux/drivers/ras/amd/atl/
H A Dreg_fields.h161 * DF2 DramBaseAddr [31:12]
162 * DF3 DramBaseAddr [31:12]
163 * DF3p5 DramBaseAddr [31:12]
171 #define DF2_BASE_ADDR GENMASK(31, 12)
183 * DF2 DramHoleBase [31:24]
184 * DF3 DramHoleBase [31:24]
185 * DF3p5 DramHoleBase [31:24]
188 * DF4 DramHoleBase [31:24]
189 * DF4p5 DramHoleBase [31:24]
191 #define DF_DRAM_HOLE_BASE_MASK GENMASK(31, 24)
[all …]
/linux/arch/alpha/include/asm/
H A Dxor.h402 ldq $31, 0($17) \n\
403 ldq $31, 0($18) \n\
405 ldq $31, 64($17) \n\
406 ldq $31, 64($18) \n\
408 ldq $31, 128($17) \n\
409 ldq $31, 128($18) \n\
411 ldq $31, 192($17) \n\
412 ldq $31, 192($18) \n\
435 ldq $31,256($17) \n\
437 ldq $31,256($18) \n\
[all …]
/linux/tools/testing/selftests/hid/tests/
H A Dtest_multitouch.py492 …31 81 02 45 00 c0 c0 05 0d 09 06 15 00 26 ff 00 a1 01 85 02 75 08 95 3f 09 00 82 02 01 95 3f 09 00…
1112 …31 15 00 26 ff 7f 35 00 46 00 00 95 02 75 10 81 02 c0 a1 02 15 00 26 ff 00 09 01 95 39 75 08 81 01…
1123 …31 15 00 26 ff 7f 35 00 46 00 00 95 02 75 10 81 02 c0 a1 02 15 00 26 ff 00 09 01 95 39 75 08 81 03…
1134 …31 26 ff 2b 46 f1 01 81 02 46 00 00 c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02…
1171 …31 46 60 11 81 02 c0 09 22 a1 02 05 0d 35 00 45 00 55 00 65 00 09 42 25 01 75 01 81 02 09 32 81 02…
1181 …31 26 ff 2b 46 f1 01 81 02 46 00 00 c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02…
1190 …55 0e 65 11 35 00 75 10 46 56 0a 26 ff 0f 09 30 81 02 46 b2 05 26 ff 0f 09 31 81 02 05 0d 75 08 85…
1199 …31 81 02 c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 95 06 81 03 75 08 09 51 95…
1208 …31 26 ff 29 46 39 02 81 02 46 00 00 c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02…
1217 …31 15 00 26 ff 7f 35 00 46 ff 7f 75 10 95 02 81 02 05 0d 09 33 15 00 26 ff 00 35 00 46 ff 00 75 08…
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
22 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
41 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
61 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
75 #define MT_RXD6_QOS_CTL GENMASK(31, 16)
77 #define MT_RXD7_HT_CONTROL GENMASK(31, 0)
79 #define MT_RXV1_ACID_DET_H BIT(31)
95 #define MT_RXV2_SEL_ANT BIT(31)
101 #define MT_RXV3_WB_RSSI GENMASK(31, 24)
104 #define MT_RXV4_RCPI3 GENMASK(31, 24)
[all …]
/linux/drivers/net/ipa/reg/
H A Dipa_reg-v3.1.c18 /* Bits 5-31 reserved */
41 /* Bits 17-31 reserved */
54 /* Bits 25-31 reserved */
61 [MEM_BADDR] = GENMASK(31, 16),
69 /* Bits 8-31 reserved */
89 /* Bits 13-31 reserved */
101 /* Bits 17-31 reserved */
113 /* Bits 5-31 reserved */
122 [Y_MAX_LIM] = GENMASK(31, 24),
132 [Y_MAX_LIM] = GENMASK(31, 24),
[all …]
H A Dipa_reg-v5.0.c16 [PROD_LOWEST] = GENMASK(31, 24),
47 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
84 [DRBIP] = BIT(31),
96 /* Bits 29-31 reserved */
103 [MEM_BADDR] = GENMASK(31, 16),
111 /* Bits 8-31 reserved */
121 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
134 /* Bits 5-31 reserved */
141 /* Bits 18-31 reserved */
159 /* Bits 21-31 reserved */
[all …]
H A Dipa_reg-v5.5.c16 [PROD_LOWEST] = GENMASK(31, 24),
46 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
83 [DRBIP] = BIT(31),
95 /* Bits 29-31 reserved */
102 [MEM_BADDR] = GENMASK(31, 16),
110 /* Bits 8-31 reserved */
120 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
133 /* Bits 5-31 reserved */
140 /* Bits 18-31 reserved */
158 /* Bits 21-31 reserved */
[all …]
H A Dipa_reg-v3.5.1.c18 /* Bits 5-31 reserved */
46 /* Bits 22-31 reserved */
59 /* Bits 25-31 reserved */
66 [MEM_BADDR] = GENMASK(31, 16),
74 /* Bits 8-31 reserved */
94 /* Bits 13-31 reserved */
106 /* Bits 17-31 reserved */
118 /* Bits 5-31 reserved */
127 /* Bits 5-31 reserved */
140 /* Bits 28-31 reserved */
[all …]
H A Dipa_reg-v4.2.c31 /* Bits 21-31 reserved */
67 /* Bits 30-31 reserved */
80 /* Bits 25-31 reserved */
87 [MEM_BADDR] = GENMASK(31, 16),
95 /* Bits 8-31 reserved */
105 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
118 /* Bits 13-31 reserved */
131 /* Bits 13-31 reserved */
143 /* Bits 17-31 reserved */
155 /* Bits 9-31 reserved */
[all …]
H A Dipa_reg-v4.5.c32 /* Bits 22-31 reserved */
69 /* Bit 31 reserved */
82 /* Bits 25-31 reserved */
89 [MEM_BADDR] = GENMASK(31, 16),
97 /* Bits 8-31 reserved */
107 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
120 /* Bits 13-31 reserved */
130 /* Bits 18-31 reserved */
148 /* Bits 18-31 reserved */
161 /* Bits 28-31 reserved */
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.h7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
27 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
41 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
61 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
72 #define MT_RXV1_VHTA1_B5_B4 GENMASK(31, 30)
86 #define MT_RXV2_VHTA1_B16_B6 GENMASK(31, 21)
89 #define MT_RXV3_F_AGC1_CAL_GAIN GENMASK(31, 29)
100 #define MT_RXV4_F_AGC_CAL_GAIN GENMASK(31, 29)
107 #define MT_RXV5_LTF_SNR0 GENMASK(31, 26)
130 #define MT_TXD0_P_IDX BIT(31)
[all …]
/linux/drivers/gpu/drm/msm/registers/adreno/
H A Dadreno_pm4.xml140 <value name="CCU_END_RESOLVE_GROUP" value="31" variants="A7XX"/>
688 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
692 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
768 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
772 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
775 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
822 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
825 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
828 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
841 <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
[all …]
/linux/arch/arc/include/asm/
H A Dbitops.h23 * This is a pure count, so (1-32) or (0-31) doesn't apply
25 * clz(0x8000_0000) = 0, clz(0xFFFF_FFFF)=0, clz(0) = 32, clz(1) = 31
83 * __fls: Similar to fls, but zero based (0-31)
100 * __ffs: Similar to ffs, but zero based (0-31)
122 " fls.f %0, %1 \n" /* 0:31; 0(Z) if src 0 */ in fls()
123 " add.nz %0, %0, 1 \n" /* 0:31 -> 1:32 */ in fls()
132 * __fls: Similar to fls, but zero based (0-31). Also 0 if no bit set
149 " ffs.f %0, %1 \n" /* 0:31; 31(Z) if src 0 */ in ffs()
150 " add.nz %0, %0, 1 \n" /* 0:31 -> 1:32 */ in ffs()
151 " mov.z %0, 0 \n" /* 31(Z)-> 0 */ in ffs()
[all …]

12345678910>>...167