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/linux/drivers/media/platform/ti/omap3isp/
H A Dnoise_filter_table.h16 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31,
17 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31
/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl502d.h30 …_WAIT_FOR_IDLE_V 31:0
33 …_SET_DST_CONTEXT_DMA_HANDLE 31:0
36 …_SET_SRC_CONTEXT_DMA_HANDLE 31:0
39 …_SET_SEMAPHORE_CONTEXT_DMA_HANDLE 31:0
78 …_SET_DST_PITCH_V 31:0
81 …_SET_DST_WIDTH_V 31:0
84 …_SET_DST_HEIGHT_V 31:0
90 …_SET_DST_OFFSET_LOWER_V 31:0
130 …_SET_SRC_PITCH_V 31:0
133 …_SET_SRC_WIDTH_V 31:0
[all …]
H A Dcl902d.h31 …_WAIT_FOR_IDLE_V 31:0
82 …_SET_DST_PITCH_V 31:0
85 …_SET_DST_WIDTH_V 31:0
88 …_SET_DST_HEIGHT_V 31:0
94 …_SET_DST_OFFSET_LOWER_V 31:0
146 …_SET_SRC_PITCH_V 31:0
149 …_SET_SRC_WIDTH_V 31:0
152 …_SET_SRC_HEIGHT_V 31:0
158 …_SET_SRC_OFFSET_LOWER_V 31:0
224 …_SET_RENDER_SOLID_PRIM_COLOR_V 31:0
[all …]
H A Dcl5039.h30 …_NO_OPERATION_V 31:0
33 …_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0
36 …_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0
39 …_SET_CONTEXT_DMA_BUFFER_OUT_HANDLE 31:0
65 …_SET_SRC_WIDTH_V 31:0
68 …_SET_SRC_HEIGHT_V 31:0
71 …_SET_SRC_DEPTH_V 31:0
74 …_SET_SRC_LAYER_V 31:0
78 …_SET_SRC_ORIGIN_Y 31:16
104 …_SET_DST_WIDTH_V 31:0
[all …]
/linux/arch/powerpc/lib/
H A Dfeature-fixups-test.S48 or 31,31,31
52 or 31,31,31
68 or 31,31,31
69 or 31,31,31
83 or 31,31,31
84 or 31,31,31
98 or 31,31,31
99 or 31,31,31
302 or 31,31,31; \
303 or 31,31,31; \
[all …]
/linux/arch/powerpc/xmon/
H A Dppc-opc.c1017 else if (value >= 24 && value <= 31) in insert_rx()
1046 else if (value >= 24 && value <= 31) in insert_ry()
1588 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) in insert_mbe()
1629 ret |= 1L << (31 - i); in extract_mbe()
1637 ret &= ~(1L << (31 - i)); in extract_mbe()
3158 {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3160 {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3687 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3747 {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
4592 {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
[all …]
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_ethtool.c95 .start = 31,
265 .start = 31,
272 .start = 31,
279 .start = 31,
286 .start = 31,
293 .start = 31,
300 .start = 31,
307 .start = 31,
314 .start = 31,
321 .start = 31,
[all …]
/linux/tools/arch/x86/kcpuid/
H A Dcpuid.csv15 0x0, 0, eax, 31:0, max_std_leaf , Highest standard CPUID leaf
16 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3
17 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11
18 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7
32 0x1, 0, ebx, 31:24, local_apic_id , Initial local APIC physical ID
63 0x1, 0, ecx, 31, guest_status , System is running as guest; (para-)virtualized system
93 0x1, 0, edx, 31, pbe , Pending Break Enable
102 0x2, 0, eax, 31, eax_invalid , Descriptors 1-3 are invalid if set
107 0x2, 0, ebx, 31, ebx_invalid , Descriptors 4-7 are invalid if set
112 0x2, 0, ecx, 31, ecx_invali
[all...]
/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-vsp1-hgo.rst52 - [31:24]
72 - :cspan:`4` R/Cr/H sum [31:0]
74 - :cspan:`4` G/Y/S sum [31:0]
76 - :cspan:`4` B/Cb/V sum [31:0]
78 - :cspan:`4` R/Cr/H bin 0 [31:0]
82 - :cspan:`4` R/Cr/H bin 63 [31:0]
84 - :cspan:`4` G/Y/S bin 0 [31:0]
88 - :cspan:`4` G/Y/S bin 63 [31:0]
90 - :cspan:`4` B/Cb/V bin 0 [31:0]
94 - :cspan:`4` B/Cb/V bin 63 [31:0]
[all …]
/linux/lib/crypto/powerpc/
H A Dpoly1305-p10le_64.S114 SAVE_GPR 31, 248, 1
128 SAVE_VRS 31, 176, 9
147 SAVE_VSX 31, 464, 9
163 RESTORE_VRS 31, 176, 9
182 RESTORE_VSX 31, 464, 9
201 RESTORE_GPR 31, 248, 1
354 xxlxor 31, 31, 31
443 vsrd 10, 14, 31
444 vsrd 11, 17, 31
448 vsrd 12, 18, 31
[all …]
/linux/drivers/video/fbdev/nvidia/
H A Dnv_dma.h58 #define SURFACE_PITCH_DST 31:16
75 #define CLIP_POINT_Y 31:16
78 #define CLIP_SIZE_HEIGHT 31:16
89 #define LINE_LINES_POINT0_Y 31:16
95 #define BLIT_POINT_SRC_Y 31:16
98 #define BLIT_POINT_DST_Y 31:16
101 #define BLIT_SIZE_HEIGHT 31:16
112 #define RECT_SOLID_RECTS_X 31:16
118 #define RECT_EXPAND_ONE_COLOR_CLIP_POINT0_Y 31:16
124 #define RECT_EXPAND_ONE_COLOR_SIZE_HEIGHT 31:16
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-ciu2-defs.h31 #define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31)…
32 #define CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31)…
33 …EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull)
34 …N_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull)
35 …N_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull)
36 …X_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull)
37 …X_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull)
38 …X_IP3_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull)
39 …X_IP3_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull)
41 …W_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull)
[all …]
H A Dcvmx-pexp-defs.h31 #define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31…
68 …I_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12)
92 #define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) …
93 …_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16)
94 …NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16)
95 …_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16)
96 …PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16)
97 #define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31)…
98 …_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16)
99 …NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16)
[all …]
/linux/drivers/ras/amd/atl/
H A Dreg_fields.h161 * DF2 DramBaseAddr [31:12]
162 * DF3 DramBaseAddr [31:12]
163 * DF3p5 DramBaseAddr [31:12]
171 #define DF2_BASE_ADDR GENMASK(31, 12)
183 * DF2 DramHoleBase [31:24]
184 * DF3 DramHoleBase [31:24]
185 * DF3p5 DramHoleBase [31:24]
188 * DF4 DramHoleBase [31:24]
189 * DF4p5 DramHoleBase [31:24]
191 #define DF_DRAM_HOLE_BASE_MASK GENMASK(31, 24)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac3_mac.h31 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
37 #define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)
56 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
74 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
88 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
102 #define MT_RXD10_QOS_CTL GENMASK(31, 16)
104 #define MT_RXD11_HT_CONTROL GENMASK(31, 0)
114 #define MT_PRXV_RCPI3 GENMASK(31, 24)
147 #define MT_CRXV_HE_RU3_L GENMASK(31, 27)
167 #define MT_CRXV_EHT_RU3_L GENMASK(31, 27)
[all …]
/linux/tools/testing/selftests/hid/tests/
H A Dtest_multitouch.py496 …31 81 02 45 00 c0 c0 05 0d 09 06 15 00 26 ff 00 a1 01 85 02 75 08 95 3f 09 00 82 02 01 95 3f 09 00…
1210 …31 15 00 26 ff 7f 35 00 46 00 00 95 02 75 10 81 02 c0 a1 02 15 00 26 ff 00 09 01 95 39 75 08 81 01…
1221 …31 15 00 26 ff 7f 35 00 46 00 00 95 02 75 10 81 02 c0 a1 02 15 00 26 ff 00 09 01 95 39 75 08 81 03…
1232 …31 26 ff 2b 46 f1 01 81 02 46 00 00 c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02…
1269 …31 46 60 11 81 02 c0 09 22 a1 02 05 0d 35 00 45 00 55 00 65 00 09 42 25 01 75 01 81 02 09 32 81 02…
1279 …31 26 ff 2b 46 f1 01 81 02 46 00 00 c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02…
1288 …55 0e 65 11 35 00 75 10 46 56 0a 26 ff 0f 09 30 81 02 46 b2 05 26 ff 0f 09 31 81 02 05 0d 75 08 85…
1297 …31 81 02 c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 95 06 81 03 75 08 09 51 95…
1306 …31 26 ff 29 46 39 02 81 02 46 00 00 c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02…
1315 …31 15 00 26 ff 7f 35 00 46 ff 7f 75 10 95 02 81 02 05 0d 09 33 15 00 26 ff 00 35 00 46 ff 00 75 08…
[all …]
/linux/drivers/net/ipa/reg/
H A Dipa_reg-v3.1.c18 /* Bits 5-31 reserved */
41 /* Bits 17-31 reserved */
54 /* Bits 25-31 reserved */
61 [MEM_BADDR] = GENMASK(31, 16),
69 /* Bits 8-31 reserved */
89 /* Bits 13-31 reserved */
101 /* Bits 17-31 reserved */
113 /* Bits 5-31 reserved */
122 [Y_MAX_LIM] = GENMASK(31, 24),
132 [Y_MAX_LIM] = GENMASK(31, 24),
[all …]
H A Dipa_reg-v5.0.c16 [PROD_LOWEST] = GENMASK(31, 24),
47 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
84 [DRBIP] = BIT(31),
96 /* Bits 29-31 reserved */
103 [MEM_BADDR] = GENMASK(31, 16),
111 /* Bits 8-31 reserved */
121 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
134 /* Bits 5-31 reserved */
141 /* Bits 18-31 reserved */
159 /* Bits 21-31 reserved */
[all …]
H A Dipa_reg-v5.5.c16 [PROD_LOWEST] = GENMASK(31, 24),
46 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
83 [DRBIP] = BIT(31),
95 /* Bits 29-31 reserved */
102 [MEM_BADDR] = GENMASK(31, 16),
110 /* Bits 8-31 reserved */
120 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
133 /* Bits 5-31 reserved */
140 /* Bits 18-31 reserved */
158 /* Bits 21-31 reserved */
[all …]
H A Dipa_reg-v3.5.1.c18 /* Bits 5-31 reserved */
46 /* Bits 22-31 reserved */
59 /* Bits 25-31 reserved */
66 [MEM_BADDR] = GENMASK(31, 16),
74 /* Bits 8-31 reserved */
94 /* Bits 13-31 reserved */
106 /* Bits 17-31 reserved */
118 /* Bits 5-31 reserved */
127 /* Bits 5-31 reserved */
140 /* Bits 28-31 reserved */
[all …]
H A Dipa_reg-v4.2.c31 /* Bits 21-31 reserved */
67 /* Bits 30-31 reserved */
80 /* Bits 25-31 reserved */
87 [MEM_BADDR] = GENMASK(31, 16),
95 /* Bits 8-31 reserved */
105 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
118 /* Bits 13-31 reserved */
131 /* Bits 13-31 reserved */
143 /* Bits 17-31 reserved */
155 /* Bits 9-31 reserved */
[all …]
H A Dipa_reg-v4.5.c32 /* Bits 22-31 reserved */
69 /* Bit 31 reserved */
82 /* Bits 25-31 reserved */
89 [MEM_BADDR] = GENMASK(31, 16),
97 /* Bits 8-31 reserved */
107 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
120 /* Bits 13-31 reserved */
130 /* Bits 18-31 reserved */
148 /* Bits 18-31 reserved */
161 /* Bits 28-31 reserved */
[all …]
H A Dipa_reg-v4.11.c38 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
75 [DRBIP] = BIT(31),
88 /* Bits 25-31 reserved */
95 [MEM_BADDR] = GENMASK(31, 16),
103 /* Bits 8-31 reserved */
113 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
126 /* Bits 13-31 reserved */
136 /* Bits 18-31 reserved */
155 /* Bits 19-31 reserved */
168 /* Bits 28-31 reserved */
[all …]
/linux/arch/arm64/tools/
H A Dsysreg61 Field 31:0 DTRRX
65 Res0 63:31
77 Field 31 TFO
101 Field 31:0 DTRTX
112 Field 31:0 OPCODE
117 Field 31:0 EDECCR
206 UnsignedEnum 31:30 P15
294 Field 31:20 ProductID
302 Field 31:21 ARCHITECT
312 Field 31 F0V
[all …]
/linux/drivers/clk/eswin/
H A Dclk-eic7700.c209 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_GPU_GRAY, 31, 0),
238 EIC7700_REG_OFFSET_SPLL0_CFG_2, 31, 0),
740 EIC7700_REG_OFFSET_DSP_ACLK, 31, 0),
776 EIC7700_REG_OFFSET_U84, 31, 0),
796 EIC7700_REG_OFFSET_NOC, 31, 0),
799 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI, 31, 0),
803 31, 0),
806 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_CORE, 31,
810 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_BUSCLK, 31,
814 CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_CORE, 31,
[all …]

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