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/linux/Documentation/hwmon/
H A Ddme1737.rst18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
[all …]
H A Dltc4245.rst10 Addresses scanned: 0x20-0x3f
20 -----------
28 -----------
38 $ echo ltc4245 0x23 > /sys/bus/i2c/devices/i2c-1/new_device
42 -------------
44 The LTC4245 has built-in limits for over and under current warnings. This
48 into the values specified in the sysfs-interface document. The current readings
52 in1_input 12v input voltage (mV)
53 in2_input 5v input voltage (mV)
54 in3_input 3v input voltage (mV)
[all …]
/linux/lib/crypto/
H A Dblake2s.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
20 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
21 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
22 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
23 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
24 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
25 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
26 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
27 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
[all …]
/linux/arch/arm/crypto/
H A Dblake2b-neon-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 // M_0-M_3 are occasionally used for other purposes too.
50 // rotation amounts with NEON. (On Cortex-A53 it's the same speed as
51 // vshr.u64 + vsli.u64, while on Cortex-A7 it's faster.)
53 .byte 3, 4, 5, 6, 7, 0, 1, 2
55 .byte 2, 3, 4, 5, 6, 7, 0, 1
63 // Execute one round of BLAKE2b by updating the state matrix v[0..15] in the
64 // NEON registers q0-q7. The message block is in q8..q15 (M_0-M_15). The stack
65 // pointer points to a 32-byte aligned buffer containing a copy of q8 and q9
66 // (M_0-M_3), so that they can be reloaded if they are used as temporary
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-packed-hsv.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _packed-hsv:
13 depends on the hsv-encoding used, see :ref:`colorspaces`.
14 The *saturation* (s) and the *value* (v) are measured in percentage of the
29 .. _packed-hsv-formats:
31 .. flat-table:: Packed HSV Image Formats
32 :header-rows: 2
33 :stub-columns: 0
35 * - Identifier
36 - Code
[all …]
/linux/drivers/iio/dac/
H A Dad3552r.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * AD3552R Digital <-> Analog converters common header
5 * Copyright 2021-2024 Analog Devices Inc.
16 #define AD3552R_MASK_ADDR_ASCENSION BIT(5)
20 #define AD3552R_MASK_SHORT_INSTRUCTION BIT(3)
23 #define AD3552R_MASK_CUSTOM_MODES GENMASK(3, 2)
31 #define AD3552R_MASK_DEVICE_REVISION GENMASK(3, 0)
44 #define AD3552R_MASK_STRICT_REGISTER_ACCESS BIT(5)
47 #define AD3552R_MASK_CLOCK_COUNTING_ERROR BIT(5)
48 #define AD3552R_MASK_INVALID_OR_NO_CRC BIT(3)
[all …]
/linux/lib/crypto/arm/
H A Dblake2s-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
18 // load the words on-demand.
62 // Execute a quarter-round of BLAKE2s by mixing two columns or two diagonals.
64 // columns/diagonals. s0-s1 are the word offsets to the message words the first
65 // column/diagonal needs, and likewise s2-s3 for the second column/diagonal.
116 // Execute one round of BLAKE2s by updating the state matrix v[0..15]. v[0..9]
118 // spilling v[8..9], then to v[9..15], then to the message block. r10-r12 and
119 // r14 are free to use. The macro arguments s0-s15 give the order in which the
135 // (v[0], v[4], v[8], v[12]) and (v[1], v[5], v[9], v[13]).
136 __ldrd r10, r11, sp, 16 // load v[12] and v[13]
[all …]
/linux/tools/testing/selftests/net/forwarding/
H A Drouter_multicast.sh2 # SPDX-License-Identifier: GPL-2.0
4 # +------------------+
5 # | H1 (v$h1) |
9 # +-------------|----+
11 # +-------------|-------------------------------+
17 # | 2001:db8:2::1/64 2001:db8:3::1/64 |
20 # +--------------|--------------------------|---+
23 # +--------------|---+ +--------------|---+
24 # | H2 (v$h2) | | | H3 (v$h3) | |
27 # | 2001:db8:2::2/64 | | 2001:db8:3::2/64 |
[all …]
/linux/tools/testing/selftests/rseq/
H A Drseq-arm-bits.h1 /* SPDX-License-Identifier: LGPL-2.1 OR MIT */
3 * rseq-arm-bits.h
5 * (C) Copyright 2016-2022 - Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
8 #include "rseq-bits-template.h"
14 int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int c… in RSEQ_TEMPLATE_IDENTIFIER()
26 RSEQ_ASM_STORE_RSEQ_CS(1, 3f, rseq_cs) in RSEQ_TEMPLATE_IDENTIFIER()
28 RSEQ_INJECT_ASM(3) in RSEQ_TEMPLATE_IDENTIFIER()
29 "ldr r0, %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
35 "ldr r0, %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
40 "str %[newv], %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
[all …]
H A Drseq-mips-bits.h1 /* SPDX-License-Identifier: LGPL-2.1 OR MIT */
5 * (C) Copyright 2016-2022 - Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
8 #include "rseq-bits-template.h"
14 int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int c… in RSEQ_TEMPLATE_IDENTIFIER()
26 RSEQ_ASM_STORE_RSEQ_CS(1, 3f, rseq_cs) in RSEQ_TEMPLATE_IDENTIFIER()
28 RSEQ_INJECT_ASM(3) in RSEQ_TEMPLATE_IDENTIFIER()
29 LONG_L " $4, %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
34 LONG_L " $4, %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
38 LONG_S " %[newv], %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
40 RSEQ_INJECT_ASM(5) in RSEQ_TEMPLATE_IDENTIFIER()
[all …]
H A Drseq-x86-bits.h1 /* SPDX-License-Identifier: LGPL-2.1 OR MIT */
3 * rseq-x86-bits.h
5 * (C) Copyright 2016-2022 - Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
8 #include "rseq-bits-template.h"
16 int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int c… in RSEQ_TEMPLATE_IDENTIFIER()
21 RSEQ_ASM_DEFINE_TABLE(3, 1f, 2f, 4f) /* start, commit, abort */ in RSEQ_TEMPLATE_IDENTIFIER()
28 RSEQ_ASM_STORE_RSEQ_CS(1, 3b, RSEQ_ASM_TP_SEGMENT:RSEQ_CS_OFFSET(%[rseq_offset])) in RSEQ_TEMPLATE_IDENTIFIER()
30 RSEQ_INJECT_ASM(3) in RSEQ_TEMPLATE_IDENTIFIER()
31 "cmpq %[v], %[expect]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
36 "cmpq %[v], %[expect]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
[all …]
H A Drseq-arm64-bits.h1 /* SPDX-License-Identifier: LGPL-2.1 OR MIT */
3 * rseq-arm64-bits.h
5 * (C) Copyright 2016-2022 - Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
6 * (C) Copyright 2018 - Will Deacon <will.deacon@arm.com>
9 #include "rseq-bits-template.h"
15 int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int c… in RSEQ_TEMPLATE_IDENTIFIER()
20 RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) in RSEQ_TEMPLATE_IDENTIFIER()
28 RSEQ_INJECT_ASM(3) in RSEQ_TEMPLATE_IDENTIFIER()
29 RSEQ_ASM_OP_CMPEQ(v, expect, %l[cmpfail]) in RSEQ_TEMPLATE_IDENTIFIER()
33 RSEQ_ASM_OP_CMPEQ(v, expect, %l[error2]) in RSEQ_TEMPLATE_IDENTIFIER()
[all …]
H A Drseq-s390-bits.h1 /* SPDX-License-Identifier: LGPL-2.1 OR MIT */
3 #include "rseq-bits-template.h"
9 int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int c… in RSEQ_TEMPLATE_IDENTIFIER()
14 RSEQ_ASM_DEFINE_TABLE(3, 1f, 2f, 4f) /* start, commit, abort */ in RSEQ_TEMPLATE_IDENTIFIER()
21 RSEQ_ASM_STORE_RSEQ_CS(1, 3b, rseq_cs) in RSEQ_TEMPLATE_IDENTIFIER()
23 RSEQ_INJECT_ASM(3) in RSEQ_TEMPLATE_IDENTIFIER()
24 LONG_CMP " %[expect], %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
29 LONG_CMP " %[expect], %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
33 LONG_S " %[newv], %[v]\n\t" in RSEQ_TEMPLATE_IDENTIFIER()
35 RSEQ_INJECT_ASM(5) in RSEQ_TEMPLATE_IDENTIFIER()
[all …]
H A Drseq-riscv-bits.h1 /* SPDX-License-Identifier: LGPL-2.1 OR MIT */
3 #include "rseq-bits-template.h"
9 int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int c… in RSEQ_TEMPLATE_IDENTIFIER()
13 __asm__ __volatile__ goto(RSEQ_ASM_DEFINE_TABLE(1, 2f, 3f, 4f) in RSEQ_TEMPLATE_IDENTIFIER()
21 RSEQ_INJECT_ASM(3) in RSEQ_TEMPLATE_IDENTIFIER()
22 RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]") in RSEQ_TEMPLATE_IDENTIFIER()
26 RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]") in RSEQ_TEMPLATE_IDENTIFIER()
28 RSEQ_ASM_OP_FINAL_STORE(newv, v, 3) in RSEQ_TEMPLATE_IDENTIFIER()
29 RSEQ_INJECT_ASM(5) in RSEQ_TEMPLATE_IDENTIFIER()
33 [current_cpu_id] "m" (rseq_get_abi()->RSEQ_TEMPLATE_CPU_ID_FIELD), in RSEQ_TEMPLATE_IDENTIFIER()
[all …]
/linux/drivers/media/platform/sunxi/sun6i-csi/
H A Dsun6i_csi_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2011-2018 Magewell Electronics Co., Ltd. (Nanjing)
5 * Copyright 2021-2022 Bootlin
18 #define SUN6I_CSI_EN_PTN_CYCLE(v) (((v) << 16) & GENMASK(23, 16)) argument
21 #define SUN6I_CSI_EN_CLK_CNT_SPL_VSYNC BIT(3)
29 #define SUN6I_CSI_IF_CFG_FIELD_DT_PCLK_SHIFT(v) (((v) << 24) & GENMASK(27, 24)) argument
47 #define SUN6I_CSI_IF_CFG_DATA_WIDTH_8_PLUS_2 (3 << 8)
54 #define SUN6I_CSI_IF_CFG_IF_CSI_BT1120 (5 << 0)
57 #define SUN6I_CSI_CAP_MASK(v) (((v) << 2) & GENMASK(5, 2)) argument
70 #define SUN6I_CSI_CH_CFG_PAD_VAL(v) (((v) << 24) & GENMASK(31, 24)) argument
[all …]
/linux/arch/alpha/kernel/
H A Dentry.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Kernel entry-points.
8 #include <asm/asm-offsets.h>
35 .size \func, . - \func
39 * This defines the normal kernel pt-regs layout.
41 * regs 9-15 preserved by C code
42 * regs 16-18 saved by PAL-code
43 * regs 29-30 saved and set up by PAL-code
44 * JRP - Save regs 16-18 in a special area of the stack, so that
45 * the palcode-provided values are available to the signal handler.
[all …]
/linux/drivers/comedi/drivers/
H A Ddt2815.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
20 * [0] - I/O port base base address
21 * [1] - IRQ (unused)
22 * [2] - Voltage unipolar/bipolar configuration
23 * 0 == unipolar 5V (0V -- +5V)
24 * 1 == bipolar 5V (-5V -- +5V)
25 * [3] - Current offset configuration
26 * 0 == disabled (0mA -- +32mAV)
27 * 1 == enabled (+4mA -- +20mAV)
[all …]
/linux/sound/soc/codecs/
H A Dcs43130.h1 /* SPDX-License-Identifier: GPL-2.0-only */
45 #define CS43130_PLL_SET_3 0x030003 /* PLL Setting 3 */
47 #define CS43130_PLL_SET_5 0x030005 /* PLL Setting 5 */
88 #define CS43130_DSD_PATH_CTL_3 0x070006 /* DSD Proc Path Sig Ctl 3 */
119 #define CS43130_INT_STATUS_3 0x0F0002 /* Interrupt Status 3 */
121 #define CS43130_INT_STATUS_5 0x0F0004 /* Interrupt Status 5 */
124 #define CS43130_INT_MASK_3 0x0F0012 /* Interrupt Mask 3 */
126 #define CS43130_INT_MASK_5 0x0F0014 /* Interrupt Mask 5 */
141 #define CS43130_HP_DETECT_INV_SHIFT 5
147 #define CS43130_HP_UNPLUG_INT_SHIFT 5
[all …]
/linux/drivers/staging/media/sunxi/sun6i-isp/
H A Dsun6i_isp_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2021-2022 Bootlin
21 #define SUN6I_ISP_FE_CFG_SRC0_MODE(v) (((v) << 8) & GENMASK(9, 8)) argument
22 #define SUN6I_ISP_FE_CFG_SRC1_MODE(v) (((v) << 16) & GENMASK(17, 16)) argument
28 #define SUN6I_ISP_FE_CTRL_LUT_UPDATE BIT(3)
30 #define SUN6I_ISP_FE_CTRL_GAMMA_UPDATE BIT(5)
33 #define SUN6I_ISP_FE_CTRL_OUTPUT_SPEED_CTRL(v) (((v) << 16) & GENMASK(17, 16)) argument
40 #define SUN6I_ISP_FE_INT_EN_PARA_LOAD BIT(3)
42 #define SUN6I_ISP_FE_INT_EN_SRC1_FIFO BIT(5)
51 #define SUN6I_ISP_FE_INT_STA_PARA_LOAD BIT(3)
[all …]
/linux/drivers/gpu/drm/exynos/
H A Dregs-scaler.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* drivers/gpu/drm/exynos/regs-scaler.h
58 * 3 90 94 98 9c 170 174 178 17c
60 * 5 b0 b4 b8 bc 190 194 198 19c
72 * 3 108 10c 1e8 1ec
74 * 5 118 11c 1f8 1fc
127 #define SCALER_MASK(hi_b, lo_b) ((1 << ((hi_b) - (lo_b) + 1)) - 1)
168 #define SCALER_INT_EN_ILLEGAL_SRC_Y_SPAN (1 << 5)
170 #define SCALER_INT_EN_ILLEGAL_SRC_CB_BASE (1 << 3)
196 #define SCALER_INT_STATUS_ILLEGAL_SRC_Y_SPAN (1 << 5)
[all …]
/linux/drivers/media/platform/verisilicon/
H A Drockchip_vpu2_hw_h264_dec.c1 // SPDX-License-Identifier: GPL-2.0
6 * Hertz Wong <hertz.wong@rock-chips.com>
7 * Herman Chen <herman.chen@rock-chips.com>
16 #include <media/v4l2-mem2mem.h>
28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
[all …]
/linux/arch/x86/include/asm/
H A Dperf_event_p4.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * perf-MSRs are not shared and every thread has its
17 * own perf-MSRs set)
21 #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
25 #define ARCH_P4_CNTRVAL_MASK ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
26 #define ARCH_P4_UNFLAGGED_BIT ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))
33 #define P4_ESCR_TAG_SHIFT 5
40 #define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT) argument
41 #define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT) argument
42 #define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT) argument
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos3250-rinato.dts1 // SPDX-License-Identifier: GPL-2.0
12 /dts-v1/;
14 #include "exynos4412-ppmu-common.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/clock/samsung,s2mps11.h>
22 chassis-type = "watch";
31 stdout-path = &serial_1;
40 compatible = "samsung,secure-firmware";
44 gpio-keys {
[all …]
H A Dexynos3250-monk.dts1 // SPDX-License-Identifier: GPL-2.0
12 /dts-v1/;
14 #include "exynos4412-ppmu-common.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/clock/samsung,s2mps11.h>
34 compatible = "samsung,secure-firmware";
38 gpio-keys {
39 compatible = "gpio-keys";
41 power-key {
[all …]
/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
28 mode "640x480-60"
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
41 # 8 chars 3 lines
52 mode "640x480-75"
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
[all …]

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