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/freebsd/contrib/capsicum-test/
H A DGNUmakefile3 # Set ARCH to 32 or x32 for i386/x32 ABIs
5 ARCHFLAG=-m$(ARCH)
8 EXTRA_LIBS=-lprocstat
12 PROCESSOR:=$(shell uname -p)
14 ifneq ($(wildcard /usr/lib/$(PROCESSOR)-linux-gnu),)
16 PLATFORM_LIBDIR=/usr/lib/$(PROCESSOR)-linux-gnu
19 PLATFORM_LIBDIR=$(shell gcc -v 2>&1 | grep "Configured with:" | sed 's/.*--libdir=\(\/usr\/[^ ]*\).…
24 # assumption that any installed version is 64-bit.
25 ifeq ($(ARCHFLAG),-m32)
30 ifeq ($(ARCHFLAG),-mx32)
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUGenRegisterBankInfo.def1 //===- AMDGPUGenRegisterBankInfo.def -----------------------------*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
17 None = - 1,
108 {nullptr, 0}, // Illegal power of 2 sizes
111 {&PartMappings[2], 1}, // 16
162 {0, 32, SGPRRegBank}, // 32-bit op
163 {0, 32, SGPRRegBank}, // 2x32-bit op
165 {0, 64, SGPRRegBank}, // <2x32-bit> op
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H A DVOPDInstructions.td1 //===-- VOPDInstructions.td - Vector Instruction Definitions -------
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/freebsd/sys/contrib/openzfs/config/
H A Dhost-cpu-c-abi.m41 # host-cpu-c-abi.m4 serial 11
2 dnl Copyright (C) 2002-2019 Free Software Foundation, Inc.
24 dnl contains 32-bit instructions, whereas 'sparc64' code contains 64-bit
25 dnl instructions. A process on a SPARC CPU can be in 32-bit mode or in 64-bit
36 dnl - 'arm': test __ARMEL__.
37 dnl - 'mips', 'mipsn32', 'mips64': test _MIPSEB vs. _MIPSEL.
38 dnl - 'powerpc64': test _BIG_ENDIAN vs. _LITTLE_ENDIAN.
41 dnl - Instructions that do not exist on all of these CPUs (cmpxchg,
45 dnl - Speed of execution of the common instruction set is reasonable across
66 # - 64-bit instruction set, 64-bit pointers, 64-bit 'long': x86_64.
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/freebsd/sys/dev/cfi/
H A Dcfi_core.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2012-2013, SRI International
10 * (FA8750-10-C-0237) ("CTSRD"), as part of the DARPA CRASH research
18 * 2
615 uint32_t *x32; cfi_write_block() member
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/freebsd/share/man/man7/
H A Darch.71 .\" Copyright (c) 2016-2017 The FreeBSD Foundation.
11 .\" 2. Redistributions in binary form must reproduce the above copyright
32 .Nd Architecture-specific details
40 For full details consult the processor-specific ABI supplement
86 .Bl -column -offset indent "Architecture" "Initial Release"
100 .Bl -column -offset indent "Architecture" "Initial Release" "Final Release"
128 .Bl -tag -width "Dv ILP32"
133 types machine representations all have 4-byte size.
147 Typically these are 64-bit machines, where the
153 environment, which was the historical 32-bit predecessor for 64-bit evolution.
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/freebsd/contrib/netbsd-tests/crypto/opencrypto/
H A Dh_aesctr1.c3 /*-
12 * 2. Redistributions in binary form must reproduce the above copyright
44 * 36-byte (ie, unpadded) operations.
50 unsigned char key[36]; /* Includes 32-bit nonce */
55 /* Test Vector #1: Encrypting 16 octets using AES-CTR w/ 128-bit key*/
67 /* Test Vector #2: Encrypting 32 octets using AES-CTR w/ 128-bit key */
70 0x43, 0xD6, 0xCE, 0x1F, 0x32, 0x53, 0x91, 0x63,
83 /* Test Vector #3: Encrypting 36 octets using AES-CTR w/ 128-bit key */
101 /* Test Vector #4: Encrypting 16 octets using AES-CTR w/ 192-bit key */
114 /* Test Vector #5: Encrypting 32 octets using AES-CTR w/ 192-bit key */
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterBankInfo.h1 //===- llvm/CodeGen/RegisterBankInfo.h --------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
46 /// This can be represented as a Mask of contiguous bit starting
47 /// at StartIdx bit and spanning Length bits.
57 /// from StartIdx to StartIdx + Length -1.
71 /// significant bit that this partial mapping covers.
72 unsigned getHighBitIdx() const { return StartIdx + Length - 1; } in getHighBitIdx()
101 /// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We
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/freebsd/contrib/bearssl/src/hash/
H A Dghash_ctmul32.c28 * This implementation uses 32-bit multiplications, and only the low
37 * The implementation trick that is used here is bit-reversing (bit 0
38 * is swapped with bit 31, bit 1 with bit 30, and so on). In GF(2)[X],
41 * In other words, if we bit-reverse (over 32 bits) the operands, then we
42 * bit-reverse (over 64 bits) the result.
46 * Multiplication in GF(2)[X], truncated to its low 32 bits.
75 * Bit-reverse a 32-bit word.
86 RMS(0x33333333, 2); in rev32()
101 * "normal" and "bit reversed" operands. Hence we end up with in br_ghash_ctmul32()
102 * eighteen 32-bit multiplications instead of nine. in br_ghash_ctmul32()
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/freebsd/contrib/bearssl/src/symcipher/
H A Dpoly1305_ctmul32.c34 * Implementation notes: we split the 130-bit values into ten in poly1305_inner()
35 * 13-bit words. This gives us some space for carries and allows in poly1305_inner()
36 * using only 32x32->32 multiplications, which are way faster than in poly1305_inner()
37 * 32x32->64 multiplications on the ARM Cortex-M0/M0+, and also in poly1305_inner()
38 * help in making constant-time code on the Cortex-M3. in poly1305_inner()
40 * Since we compute modulo 2^130-5, the "upper words" become in poly1305_inner()
41 * low words with a factor of 5; that is, x*2^130 = x*5 mod p. in poly1305_inner()
45 * In each loop iteration, a[] and r[] words are 13-bit each, in poly1305_inner()
58 * If there is a partial block, right-pad it with zeros. in poly1305_inner()
68 * Decode next block and apply the "high bit"; that value in poly1305_inner()
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/freebsd/contrib/wpa/src/crypto/
H A Ddh_groups.c2 * Diffie-Hellman groups
19 /* RFC 4306, B.1. Group 1 - 768 Bit MODP
20 * Generator: 2
21 * Prime: 2^768 - 2 ^704 - 1 + 2^64 * { [2^638 pi] + 149686 }
53 /* RFC 4306, B.2. Group 2 - 1024 Bit MODP
54 * Generator: 2
55 * Prime: 2^1024 - 2^960 - 1 + 2^64 * { [2^894 pi] + 129093 }
97 /* RFC 3526, 2. Group 5 - 1536 Bit MODP
98 * Generator: 2
99 * Prime: 2^1536 - 2^1472 - 1 + 2^64 * { [2^1406 pi] + 741804 }
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/freebsd/contrib/libucl/src/
H A Dmum.h25 input data by 64x64-bit multiplication and mixing hi- and low-parts
28 with the equal probability of their bit values for the
38 strings (at least up to 512-bit) on Haswell and Power7. The MUM bulk
59 /* Macro saying to use 128-bit integers implemented by GCC for some
90 probability of their bit values. They are used to randomize input
107 /* Multiply 64-bit V and P and return sum of high and low parts of the
114 /* AARCH64 needs 2 insns to calculate 128-bit result of the in _mum()
116 function doing 128x128->128 bit multiplication. The function is in _mum()
119 asm ("umulh %0, %1, %2" : "=r" (hi) : "r" (v), "r" (p)); in _mum()
126 /* Implementation of 64x64->128-bit multiplication by four 32x32->64 in _mum()
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/freebsd/crypto/openssl/crypto/ec/
H A Dec_curve.c2 * Copyright 2002-2021 The OpenSSL Project Authors. All Rights Reserved.
85 0xB4, 0x05, 0x0A, 0x85, 0x0C, 0x04, 0xB3, 0xAB, 0xF5, 0x41, 0x32, 0x56,
89 0xB7, 0x0E, 0x0C, 0xBD, 0x6B, 0xB4, 0xBF, 0x7F, 0x32, 0x13, 0x90, 0xB9,
90 0x4A, 0x03, 0xC1, 0xD3, 0x56, 0xC2, 0x11, 0x22, 0x34, 0x32, 0x80, 0xD6,
157 0x39, 0x32, 0x84, 0xAA, 0xA0, 0xDA, 0x64, 0xBA,
279 0x8E, 0x94, 0x80, 0x60, 0xF8, 0x32, 0x1B, 0x7D,
327 0x61, 0x7F, 0xAB, 0x68, 0x32, 0x57, 0x6C, 0xBB, 0xFE, 0xD5, 0x0D, 0x99,
336 0x01, 0xd9, 0xb0, 0x81, 0x32, 0x9f, 0xb5, 0x55, 0xde, 0x6e, 0xf4, 0x60,
541 0x7B, 0x6A, 0xA5, 0xD8, 0x5E, 0x57, 0x29, 0x83, 0xE6, 0xFB, 0x32, 0xA7,
607 0x12, 0x04, 0x23, 0x51, 0x37, 0x7a, 0xc5, 0xfb, 0x32,
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/freebsd/sys/dev/mii/
H A Ddp83867phy.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
12 * 2. Redistributions in binary form must reproduce the above copyright
52 #define BIT(x) (1 << (x)) macro
61 #define DP83867_RGMIICTL 0x32
65 #define DP83867_PHYSTS_LINK_UP BIT(10)
66 #define DP83867_PHYSTS_ANEG_PENDING BIT(11)
67 #define DP83867_PHYSTS_FD BIT(13)
68 #define DP83867_PHYSTS_SPEED_MASK (BIT(15) | BIT(14))
69 #define DP83867_PHYSTS_SPEED_1000 BIT(15)
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dnvidia,tegra124-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
22 const: nvidia,tegra124-mc
30 clock-names:
32 - const: mc
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/freebsd/lib/libpmc/pmu-events/arch/x86/tigerlake/
H A Dcache.json4 "CollectPEBSRecord": "2",
5 "Counter": "0,1,2,3",
8 "PEBScounters": "0,1,2,3",
9 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
15 "CollectPEBSRecord": "2",
16 "Counter": "0,1,2,3",
19 "PEBScounters": "0,1,2,3",
26 "CollectPEBSRecord": "2",
27 "Counter": "0,1,2,3",
32 "PEBScounters": "0,1,2,3",
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/freebsd/sys/contrib/dev/rtw88/
H A Dcoex.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
27 #define PARA1_H2C69_TBTT_DIV100 BIT(7)
32 #define TDMA_4SLOT BIT(8)
71 BT_MP_INFO_OP_LNA_CONSTRAINT = 0x32,
90 COEX_RSN_SCANFINISH = 2,
143 COEX_ALGO_HID = 2,
156 BPM_HFP = BIT(0),
157 BPM_HID = BIT(1),
158 BPM_A2DP = BIT(2),
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/freebsd/share/misc/
H A Dusb_hid_usages4 # - lines that do not start with a white space give the number and name of
6 # - lines that start with a white space give the number and name of
20 0x08 Multi-axis Controller
24 0x32 Z
62 0x90 D-pad Up
63 0x91 D-pad Down
64 0x92 D-pad Right
65 0x93 D-pad Left
84 2 Simulation Controls
107 0xB2 Anti-Torque Control
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/freebsd/contrib/wireguard-tools/
H A Dcurve25519-fiat32.h1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2015-2016 The fiat-crypto Authors.
4 * Copyright (C) 2018-2020 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
6 * This is a machine-generated formally verified implementation of Curve25519
7 * ECDH from: <https://github.com/mit-plv/fiat-crypto>. Though originally
9 * It is optimized for 32-bit machines and machines that cannot work efficiently
10 * with 128-bit integer types.
13 /* fe means field element. Here the field is \Z/(2^255-19). An element t,
14 * entries t[0]...t[9], represents the integer t[0]+2^26 t[1]+2^51 t[2]+2^77
15 * t[3]+2^102 t[4]+...+2^230 t[9].
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/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/
H A Dfp_lib.h1 //===-- lib/fp_lib.h - Floating-point utilities -------------------*- C -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file is a configuration header for soft-float routines in compiler-rt.
10 // This file does not provide any part of the compiler-rt interface, but defines
12 // implementation of the soft-float routines in compiler-rt.
14 // Assumes that float, double and long double correspond to the IEEE-754
18 //===----------------------------------------------------------------------===//
43 // 32x32 --> 64 bit multiply
66 // 64x64 -> 128 wide multiply for platforms that don't have such an operation;
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/freebsd/crypto/openssl/crypto/whrlpool/asm/
H A Dwp-x86_64.pl2 # Copyright 2005-2020 The OpenSSL Project Authors. All Rights Reserved.
18 # 2500 cycles per 64-byte input block on AMD64, which is *identical*
19 # to 32-bit MMX version executed on same CPU. So why did I bother?
20 # Well, it's faster than gcc 3.3.2 generated code by over 50%, and
23 # 10 - by 360%[!]... What is it with x86_64 compilers? It's not the
28 # to 32-bit MMX version, except that %r8-15 are used instead of
29 # %mm0-8. You can even notice that K[i] and S[i] are loaded to
30 # %eax:%ebx as pair of 32-bit values and not as single 64-bit one.
31 # This is done in order to avoid 64-bit shift penalties on Intel
33 # Opteron performance by compressing the table to 2KB and replacing
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/freebsd/sys/isa/
H A Dpnpreg.h1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
12 * 2. Redistributions in binary form must reproduce the above copyright
18 * 4. Neither the name of the author nor the names of any co-contributors
51 read port address bits[9:2]. Reads from this register are ignored.
57 state to compare one bit of the boards ID.
66 Bit[2] Reset CSN to 0
67 Bit[1] Return to the Wait for Key state
68 Bit[0] Reset all logical devices and restore configuration
69 registers to their power-up values.
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/freebsd/contrib/ofed/libibverbs/man/
H A Dibv_create_flow.31 .\" Licensed under the OpenIB.org BSD license (FreeBSD Variant) - See COPYING.md
2 .TH IBV_CREATE_FLOW 3 2016-03-15 libibverbs "Libibverbs Programmer's Manual"
4 ibv_create_flow, ibv_destroy_flow \- create or destroy flow steering rules
27 enum ibv_flow_attr_type type; /* Rule type - see below */
29 uint16_t priority; /* Rule priority - see below */
32 uint32_t flags; /* Extra flags for rule - see below */
44 IBV_FLOW_ATTR_ALL_DEFAULT = 0x1, /* Default unicast and multicast rule - receive all Eth traffic w…
45 IBV_FLOW_ATTR_MC_DEFAULT = 0x2, /* Default multicast rule - receive all Eth multicast traffic whi…
46 IBV_FLOW_ATTR_SNIFFER = 0x3, /* Sniffer rule - receive all port traffic */
66 IBV_FLOW_SPEC_IPV4_EXT = 0x32, /* Extended flow specification of IPv4 */
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/freebsd/sys/powerpc/powermac/
H A Dpmuvar.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
13 * 2. Redistributions in binary form must reproduce the above copyright
44 #define PMU_WRITE_PRAM 0x32 /* Write PRAM */
55 #define PMU_POWER_EVENTS 0x8f /* Send power-event commands to PMU */
62 #define PMU_ADB_POLL_OFF 0x21 /* Disable ADB auto-poll */
70 * 16bit mask enables autopolling per
80 #define PMU_INT_PCEJECT 0x04 /* PC-card eject buttons */
85 #define PMU_INT_TICK 0x80 /* 1-second tick interrupt */
89 #define PMU_POW0_OFF 0x00 /* leave bit 7 to 0 to power it OFF */
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/freebsd/crypto/openssl/demos/mac/
H A Dpoly1305.c2 * Copyright 2021-2022 The OpenSSL Project Authors. All Rights Reserved.
19 * This is a demonstration of how to compute Poly1305-AES using the OpenSSL
24 * - Poly1305 must never be used alone and must be used in conjunction with
27 * - you must never pass a nonce to the Poly1305 primitive directly;
29 * - Poly1305 exhibits catastrophic failure (that is, can be broken) if a
36 * This example uses AES, as described in the original paper, "The Poly1305-AES
38 * https://cr.yp.to/mac/poly1305-20050329.pdf
46 * These are the "r" and "k" inputs to Poly1305-AES.
55 0x01, 0x42, 0x5b, 0x62, 0x32, 0x35, 0xad, 0xd6
66 0x2a, 0xc3, 0x27, 0x5c, 0xf9, 0xd4, 0x32, 0x7e
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