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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dti,j721e-cpb-ivi-audio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
23 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
25 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
30 Clocking setup for 48KHz family:
37 Clocking setup for 44.1KHz family:
76 - description: Parent for CPB_McASP auxclk (for 48KHz)
77 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
79 - description: Parent for CPB_SCKI clock (for 48KHz)
[all...]
H A Dti,j721e-cpb-audio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
18 In order to support 48KHz and 44.1KHz family of sampling rates the parent
19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
24 48KHz family:
28 44.1KHz family:
33 48KHz family:
85 - description: Parent for CPB_McASP auxclk (for 48KHz)
86 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
88 - description: Parent for CPB_SCKI clock (for 48KHz)
[all …]
H A Dst,stm32-sai.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
148 - description: x8k, SAI parent clock for sampling rates multiple of 8kHz.
149 - description: x11k, SAI parent clock for sampling rates multiple of 11.025kHz.
160 - description: x8k, SAI parent clock for sampling rates multiple of 8kHz.
161 - description: x11k, SAI parent clock for sampling rates multiple of 11.025kHz.
H A Dfsl,micfil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
45 - description: PLL clock source for 8kHz series
46 - description: PLL clock source for 11kHz series
48 minItems: 2
57 minItems: 2
/freebsd/contrib/file/magic/scripts/
H A Dcreate_filemagic_flac6 ## >>17 belong&0xfffff0 0x2ee000 \b, 192 kHz
15 ## (16384 kHz = 32 kHz * 512 = 32 * 2^9)
17 ## (22579.2 kHz = 44.1kHz * 512 = 44.1 * 2^9)
20 ## (24576 kHz = 48 kHz * 512 = 48 * 2^9)
46 n=$(( n / 2 ))
53 ## use bc with sed to convert and format Hz to kHz
58 printf -v line ">>17\tbelong&%#-15x\t%#08x\t%s, %s kHz\n" \
/freebsd/share/man/man4/
H A Dsnd_emu10kx.410 .\" 2. Redistributions in binary form must reproduce the above copyright
76 Creative Sound Blaster Audigy 2 and Creative Sound Blaster Audigy 4 (CA0102
78 PCM support is limited to 48kHz/16 bit stereo (192kHz/24 bit part
81 Creative Sound Blaster Audigy 2 Value (CA0108 Chipset).
83 to 48kHz/16 bit stereo (192kHz/24 bit part of this chipset is not supported).
138 you will get one more DSP device that is rate-locked to 48kHz/16bit/mono.
139 This is actually 48kHz/16bit/32 channels on SB Live! cards and
140 48kHz/16bit/64channels on Audigy cards, but the current implementation of
150 .Ss SB Live! substream map (in byte offsets, each substream is 2 bytes LE)
165 .Ss Audigy substream map (in byte offsets, each substream is 2 bytes LE)
[all …]
H A Dsnd_hdspe.49 .\" 2. Redistributions in binary form must reproduce the above copyright
25 .Dd November 2, 2024
66 For ADAT ports, 8 channel, 4 channel and 2 channel formats are supported.
68 (32kHz-48kHz), 4 channels at double speed (64kHz-96kHz), and 2 channels at
69 quad speed (128kHz-192kHz).
H A Dsnd_hdsp.410 .\" 2. Redistributions in binary form must reproduce the above copyright
67 For ADAT ports, 8 channel, 4 channel and 2 channel formats are supported.
69 (32kHz-48kHz) and 4 channels at double speed (64kHz-96kHz).
70 Only the HDSP 9632 can operate at quad speed (128kHz-192kHz), ADAT is
/freebsd/contrib/file/magic/Magdir/
H A Danimation76 >>11 byte 2 \b, Release %d (non existent)
152 >8 string dvt1 \b, DVB (.DVB) over MPEG-2 Transport Stream
172 >>11 string 2 v2 [ISO 14496-12:2005]
188 >8 string jpx \b, JPEG 2000 w/ extensions (.JPX) [ISO 15444-2]
300 >8 string risx \b, Representation Index Segment for MPEG-2 TS Segments
309 >8 string sisx \b, Single Index Segment forindex MPEG-2 TS
310 >8 string ssss \b, Subsegment Index Segment used to index MPEG-2 Segments
329 >3 byte 0xBB MPEG sequence, v1/2, multiplex (missing pack header)
351 >>4 byte 2 \b, simple @ L2
421 >>12 belong 0x000001B8 \b, v1, progressive Y'CbCr 4:2:0 video
[all …]
H A Daudio14 >12 belong 2 8-bit linear PCM [REF-PCM],
43 >20 belong 2 stereo,
52 >12 lelong 2 8-bit linear PCM [REF-PCM],
81 >20 lelong 2 stereo,
180 21 string/c =!SCREAM! Screamtracker 2 module sound data
183 21 string BMOD2STM Screamtracker 2 module sound data
239 #>1080 string >/0 %.2s-channel Fasttracker "oktalyzer" module sound data
257 0 string PSID PlaySID v2.2+ (AMIGA) sidtune
294 0 string 2BIT Audio Visual Research file,
304 >22 byte =0 replay 5.485 KHz
[all …]
H A Ddolby13 >4 byte&0xc0 = 0x00 48 kHz,
14 >4 byte&0xc0 = 0x40 44.1 kHz,
15 >4 byte&0xc0 = 0x80 32 kHz,
16 # is this one used for 96 kHz?
33 >6 byte&0xe0 = 0x40 2 front/0 rear,
42 >6 byte&0xe0 = 0x80 2 front/1 rear,
46 >6 byte&0xe0 = 0xc0 2 front/2 rear,
48 >6 byte&0xe0 = 0xe0 3 front/2 rear,
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6q.dtsi25 /* kHz uV */
33 /* ARM kHz SOC-PU uV */
41 #cooling-cells = <2>;
62 /* kHz uV */
70 /* ARM kHz SOC-PU uV */
78 #cooling-cells = <2>;
91 cpu2: cpu@2 {
94 reg = <2>;
97 /* kHz uV */
105 /* ARM kHz SOC-PU uV */
[all …]
H A Dimx6q-cm-fx6.dts13 * version 2 as published by the Free Software Foundation.
176 /* kHz uV */
183 /* ARM kHz SOC-PU uV */
198 /* kHz uV */
205 /* ARM kHz SOC-PU uV */
220 /* kHz uV */
227 /* ARM kHz SOC-PU uV */
242 /* kHz uV */
249 /* ARM kHz SOC-PU uV */
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmax77620.txt16 - #interrupt-cells: is <2> and their usage is compliant to the 2 cells
36 with internal regulators. 32KHz clock can be programmed to be part of a
46 Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power
54 When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
58 and 32KHz clock get disabled at
68 regulators, GPIOs and 32kHz clocks are provided in their respective
144 #interrupt-cells = <2>;
H A Dmxs-lradc.txt17 2 ... 2048. It is used if 'fsl,ave-ctrl' > 1, counts at
18 2 kHz and its default is 2 (= 1 ms)
20 1 ... 2047. It counts at 2 kHz and its default is
31 fsl,ave-delay = <2>;
43 fsl,ave-delay = <2>;
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Drichtek,rt6245-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
36 enum: [0, 1, 2, 3]
44 enum: [0, 1, 2]
52 enum: [0, 1, 2, 3]
61 enum: [0, 1, 2]
63 Buck switch frequency selection. Each respective value means 400KHz,
64 800KHz, 1200KHz. If this property is missing then keep in chip default.
81 enable-gpios = <&gpio26 2 0>;
/freebsd/sys/contrib/device-tree/src/arm/calxeda/
H A Dhighbank.dts29 /* kHz ignored */
48 /* kHz ignored */
67 /* kHz ignored */
86 /* kHz ignored */
140 cache-level = <2>;
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Damlogic,gxbb-aoclkc.txt19 * "ext-32k-0" : external 32kHz reference #0 if any (optional)
20 * "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only)
21 * "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only)
H A Dmaxim,max77686.txt10 The MAX77686 contains three 32.768khz clock outputs that can be controlled
15 The MAX77802 contains two 32.768khz clock outputs that can be controlled
19 The MAX77686 contains one 32.768khz clock outputs that can be controlled
36 - 2: 32khz_pmic clock (max77686).
68 2. With MAX77802:
H A Dsamsung,s2mps11.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
16 The S2MPS11/13/15 and S5M8767 provide three(AP/CP/BT) buffered 32.768 kHz
17 outputs. The S2MPS14 provides two (AP/BT) buffered 32.768 KHz outputs.
/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dkontron,sl28cpld-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
17 frequencies (250Hz, 500Hz, 1kHz, 2kHz).
30 const: 2
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-ocores.txt25 Defaults to 100 KHz when the property is not specified
27 - reg-io-width : io register width in bytes (1, 2 or 4)
37 frequency is fixed at 100 KHz.
69 clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
/freebsd/sys/dev/ath/ath_hal/ar5312/
H A Dar5312_misc.c45 2; in ar5312SetLedState()
92 * If 32KHz clock exists, use it to lower power consumption during sleep
94 * Note: If clock is set to 32 KHz, delays on accessing certain
115 OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */ in ar5312SetupClock()
139 * If 32KHz clock exists, turn it off and turn back on the 32Mhz
/freebsd/sys/contrib/device-tree/Bindings/input/
H A Diqs626a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
39 enum: [0, 1, 2, 3]
45 2: Ultra-low power (ULP channel proximity sensing)
60 enum: [0, 1, 2, 3, 4, 5, 6, 7]
67 2: 28
84 enum: [0, 1, 2, 3, 4, 5, 6, 7]
91 2: Trackpad
95 6: Generic channel 2
100 enum: [0, 1, 2, 3]
107 2: Proximity or touch
[all …]
/freebsd/sys/dev/sound/pci/
H A Denvy24ht.h2 * SPDX-License-Identifier: BSD-2-Clause
13 * 2. Redistributions in binary form must reproduce the above copyright
62 /* 00: 24.576MHz(96kHz*256) */
63 /* 01: 49.152MHz(192kHz*256) */
66 #define ENVY24HT_CCSM_SCFG_ADC 0x0c /* 1-2 stereo ADC connected, S/PDIF receiver connected */
75 #define ENVY24HT_CCSM_I2S_96KHZ 0x40 /* I2S converter 96kHz sampling rate support */
76 #define ENVY24HT_CCSM_I2S_192KHZ 0x08 /* I2S converter 192kHz sampling rate support */
160 #define ENVY24HT_CHAN_PLAY_DAC3 2

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