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/linux/Documentation/userspace-api/media/v4l/
H A Dfieldseq_tb.svg26 inkscape:pageshadow="2"
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H A Dfieldseq_bt.svg26 inkscape:pageshadow="2"
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H A Dcrop.svg31 …2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 …
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/linux/Documentation/devicetree/bindings/clock/
H A Dintel,agilex5-clkmgr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
35 clkmgr: clock-controller@10d10000 {
/linux/Documentation/devicetree/bindings/sound/
H A Ddavinci-mcbsp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
73 If the property is present, tx data delay is set to 2 bit clock periods.
80 If the property is present, rx data delay is set to 2 bit clock periods.
97 mcbsp0@1d10000 {
109 <&edma0 2 1>;
/linux/arch/arm/boot/dts/samsung/
H A Dexynos54xx.dtsi41 interrupts = <1 2>,
44 <19 2>;
82 <&combiner 25 2>,
100 adc: adc@12d10000 {
H A Dexynos5420.dtsi419 ppmu_dmc0_1: ppmu@10d10000 {
599 <&adma 2>,
839 #cooling-cells = <2>;
1003 interrupts = <22 2>;
1024 interrupts = <2 0>;
1035 interrupts = <2 2>;
1077 interrupts = <27 2>;
1120 interrupts = <4 2>;
1139 interrupts = <6 2>;
1161 interrupts = <3 2>;
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-audio.dtsi154 <&edma0 2 0 0>,
278 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, /* 2 */
482 <&edma1 2 0 0>,
554 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, /* 2 */
587 aud_rec1_lpcg: clock-controller@59d10000 {
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm845.dtsi36 #address-cells = <2>;
37 #size-cells = <2>;
92 #address-cells = <2>;
109 #cooling-cells = <2>;
113 cache-level = <2>;
138 #cooling-cells = <2>;
142 cache-level = <2>;
162 #cooling-cells = <2>;
166 cache-level = <2>;
184 #cooling-cells = <2>;
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