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/linux/Documentation/devicetree/bindings/net/
H A Dibm,emac.txt5 special McMAL DMA controller, and sometimes an RGMII or ZMII
15 - compatible : compatible list, contains 2 entries, first is
45 Supported values are: "mii", "rmii", "smii", "rgmii",
47 For Axon on CAB, it is "rgmii"
55 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
56 of the RGMII device node.
57 For Axon: phandle of plb5/plb4/opb/rgmii
58 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
59 RGMII channel is used by this EMAC.
143 phy-mode = "rgmii";
[all …]
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
32 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
33 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
57 drive strength of rx_clk rgmii pad.
58 The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can
74 drive strength of rx_data/rx_ctl rgmii pad.
75 The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can
97 Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
[all …]
H A Dtesla,fsd-ethqos.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
44 - description: PERIC RGMII clock
65 - rgmii
66 - rgmii-id
67 - rgmii-rxid
68 - rgmii-txid
86 #address-cells = <2>;
87 #size-cells = <2>;
114 phy-mode = "rgmii-id";
H A Dxlnx,gmii-to-rgmii.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/xlnx,gmii-to-rgmii.yaml#
7 title: Xilinx GMII to RGMII Converter
14 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
24 const: xlnx,gmii-to-rgmii-1.0
55 compatible = "xlnx,gmii-to-rgmii-1.0";
H A Dfaraday,ftgmac100.yaml46 - rgmii
47 - rgmii-id
48 - rgmii-rxid
49 - rgmii-txid
99 interrupts = <2>;
106 interrupts = <2>;
109 phy-mode = "rgmii";
H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
85 For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
89 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
95 For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
99 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
118 1. tx clock will be inversed in MII/RGMII case,
119 2. tx clock inside MAC will be inversed relative to reference clock
128 1. rx clock will be inversed in MII/RGMII case.
129 2. reference clock will be inversed when arrived at MAC in RMII case, when
165 phy-mode = "rgmii-rxid";
H A Dti,icssg-prueth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
37 - const: tx0-2
41 - const: tx1-2
68 maxItems: 2
75 maxItems: 2
110 ti,syscon-rgmii-delay:
118 to ICSSG control register for RGMII transmit delay
185 ti,pruss-gp-mux-sel = <2>, /* MII mode */
186 <2>,
187 <2>,
[all …]
H A Dqcom,ethqos.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
38 maxItems: 2
43 - const: rgmii
68 - rgmii
99 reg-names = "stmmaceth", "rgmii";
100 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
122 phy-mode = "rgmii";
H A Dengleder,tsnep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
31 - const: txrx-2
56 - rgmii
57 - rgmii-id
79 #address-cells = <2>;
80 #size-cells = <2>;
87 phy-mode = "rgmii";
104 interrupt-names = "mac", "txrx-1", "txrx-2", "txrx-3";
107 phy-mode = "rgmii";
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
25 Media Independent Interface (GMII) or Reduced GMII (RGMII).
81 RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
88 RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
95 PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no
97 should use "rgmii-id" if internal delays are desired as this may be
98 changed in future to cause "rgmii" mode to disable delays.
104 mode 1 or 2. To ensure PHY operation, there are specific actions that
/linux/arch/powerpc/boot/dts/
H A Deiger.dts7 * License version 2. This program is licensed "as is" without
14 #address-cells = <2>;
60 #interrupt-cells = <2>;
70 #interrupt-cells = <2>;
78 cell-index = <2>;
82 #interrupt-cells = <2>;
94 #interrupt-cells = <2>;
111 #address-cells = <2>;
154 #address-cells = <2>;
163 bank-width = <2>;
[all …]
H A Dglacier.dts7 * License version 2. This program is licensed "as is" without
14 #address-cells = <2>;
61 #interrupt-cells = <2>;
71 #interrupt-cells = <2>;
79 cell-index = <2>;
83 #interrupt-cells = <2>;
95 #interrupt-cells = <2>;
122 #address-cells = <2>;
171 #address-cells = <2>;
180 bank-width = <2>;
[all …]
H A Drainier.dts10 * License version 2. This program is licensed "as is" without
18 #address-cells = <2>;
64 #interrupt-cells = <2>;
74 #interrupt-cells = <2>;
82 cell-index = <2>;
86 #interrupt-cells = <2>;
103 #address-cells = <2>;
121 num-tx-chans = <2>;
122 num-rx-chans = <2>;
149 #address-cells = <2>;
[all …]
H A Dfsp2.dts7 * License version 2. This program is licensed "as is" without
15 #address-cells = <2>;
64 #interrupt-cells = <2>;
76 #interrupt-cells = <2>;
90 #interrupt-cells = <2>;
94 cell-index = <2>;
104 #interrupt-cells = <2>;
118 #interrupt-cells = <2>;
131 #interrupt-cells = <2>;
144 #interrupt-cells = <2>;
[all …]
H A Dsequoia.dts10 * License version 2. This program is licensed "as is" without
18 #address-cells = <2>;
64 #interrupt-cells = <2>;
74 #interrupt-cells = <2>;
82 cell-index = <2>;
86 #interrupt-cells = <2>;
103 #address-cells = <2>;
133 num-tx-chans = <2>;
134 num-rx-chans = <2>;
176 #address-cells = <2>;
[all …]
/linux/drivers/net/ethernet/apm/xgene-v2/
H A Dmac.c21 u32 intf_ctrl, rgmii; in xge_mac_set_speed() local
26 rgmii = xge_rd_csr(pdata, RGMII_REG_0); in xge_mac_set_speed()
37 SET_REG_BIT(&rgmii, CFG_SPEED_125, 0); in xge_mac_set_speed()
44 SET_REG_BIT(&rgmii, CFG_SPEED_125, 0); in xge_mac_set_speed()
47 SET_REG_BITS(&mc2, INTF_MODE, 2); in xge_mac_set_speed()
48 SET_REG_BITS(&intf_ctrl, HD_MODE, 2); in xge_mac_set_speed()
49 SET_REG_BITS(&icm0, CFG_MACMODE, 2); in xge_mac_set_speed()
51 SET_REG_BIT(&rgmii, CFG_SPEED_125, 1); in xge_mac_set_speed()
60 xge_wr_csr(pdata, RGMII_REG_0, rgmii); in xge_mac_set_speed()
71 addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | in xge_mac_set_station_addr()
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
49 - rgmii
50 - rgmii-id
51 - rgmii-txid
52 - rgmii-rxid
109 port@2 {
110 reg = <2>;
125 phy-mode = "rgmii";
139 phy-mode = "rgmii";
176 t1phy2: ethernet-phy@2{
H A Darrow,xrs700x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
18 RGMII ports and one RMII port and are managed via i2c or mdio.
54 phy-mode = "rgmii-id";
56 ethernet-port@2 {
57 reg = <2>;
60 phy-mode = "rgmii-id";
65 phy-mode = "rgmii-id";
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-wqe.h10 * it under the terms of the GNU General Public License, Version 2, as
103 * - 2 = L4 Checksum Error: the L4 checksum value is
132 * - 2 = IPv4 Header Checksum Error: the IPv4 header
330 * - 2 = jabber error: the RGMII packet was too large
332 * - 3 = overrun error: the RGMII packet is longer
334 * - 4 = oversize error: the RGMII packet is longer
336 * - 5 = alignment error: the RGMII packet is not an
339 * - 6 = fragment error: the RGMII packet is shorter
341 * - 7 = GMX FCS error: the RGMII packet had an FCS
343 * - 8 = undersize error: the RGMII packet is shorter
[all …]
H A Dcvmx-helper-rgmii.h10 * it under the terms of the GNU General Public License, Version 2, as
31 * Functions for RGMII/GMII/MII initialization, configuration,
39 * Probe RGMII ports and determine the number present
43 * Returns Number of RGMII/GMII/MII ports (0-4).
49 * Put an RGMII interface in loopback mode. Internal packets sent
59 * to get RGMII to function on the supplied interface.
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c28 #define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0)
36 * cycle of the 125MHz RGMII TX clock):
37 * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3
74 * Each step is 200ps. These bits are used with external RGMII PHYs
75 * because RGMII RX only has the small window. cfg_rxclk_dly can
152 { .div = 2, .val = 2, }, in meson8b_init_rgmii_tx_clk()
192 clk_configs->fixed_div2.div = 2; in meson8b_init_rgmii_tx_clk()
220 /* enable RGMII mode */ in meson8b_set_phy_mode()
226 /* disable RGMII mode -> enables RMII mode */ in meson8b_set_phy_mode()
246 /* enable RGMII mode */ in meson_axg_set_phy_mode()
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am654-idk.dtso37 ti,pruss-gp-mux-sel = <2>, /* MII mode */
38 <2>,
39 <2>,
40 <2>, /* MII mode */
41 <2>,
42 <2>;
50 interrupts = <24 0 2>, <25 1 3>;
64 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
65 "tx1-0", "tx1-1", "tx1-2", "tx1-3",
74 phy-mode = "rgmii-id";
[all …]
/linux/drivers/net/dsa/microchip/
H A Dlan937x_main.c29 * Port 5 is connected to an RGMII interface without a PHY. The values
33 [0] = 2, /* Port 1, T1 AFE0 */
34 [1] = 3, /* Port 2, T1 AFE1 */
35 [2] = 5, /* Port 3, T1 AFE3 */
37 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */
46 [0] = 2, /* Port 1, T1 AFE0 */
47 [1] = 3, /* Port 2, T1 AFE1 */
48 [2] = 5, /* Port 3, T1 AFE3 */
50 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */
51 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */
[all …]
/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-rgmii.c10 * it under the terms of the GNU General Public License, Version 2, as
29 * Functions for RGMII/GMII/MII initialization, configuration,
46 * Probe RGMII ports and determine the number present
50 * Returns Number of RGMII/GMII/MII ports (0-4).
61 cvmx_dprintf("ERROR: RGMII initialize called in " in __cvmx_helper_rgmii_probe()
68 * GMII/MII mode. This limits us to 2 ports in __cvmx_helper_rgmii_probe()
70 num_ports = 2; in __cvmx_helper_rgmii_probe()
92 * Put an RGMII interface in loopback mode. Internal packets sent
153 * to get RGMII to function on the supplied interface.
177 /* Configure the ASX registers needed to use the RGMII ports */ in __cvmx_helper_rgmii_enable()
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dmvme7100.dts38 phy-connection-type = "rgmii-id";
45 phy1: ethernet-phy@2 {
46 reg = <2>;
58 phy-connection-type = "rgmii-id";
67 phy-connection-type = "rgmii-id";
76 phy-connection-type = "rgmii-id";
92 2 0 0xf2030000 0x00010000 // NAND Flash (8GB)

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