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/freebsd/share/man/man4/
H A Diwlwifi.42 .\" SPDX-License-Identifier: BSD-2-Clause
14 .\" 2. Redistributions in binary form must reproduce the above copyright
113 .\" awk -F\\t '{ if ($2 == "") { next; } if (seen[$2]) { next; } \
114 .\" seen[$2]=1; printf ".It\n%s\n", $2; }' iwlwifi_pci_ids_name.txt
149 Killer (R) Wireless-AC 1550 Wireless Network Adapter (9260NGW) 160MHz
155 Killer(R) Wireless-AC 1550s Wireless Network Adapter (9560D2W) 160MHz
157 Killer(R) Wireless-AC 1550i Wireless Network Adapter (9560NGW) 160MHz
159 Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)
161 Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)
165 Intel(R) Wi-Fi 6 AX200 160MHz
[all …]
H A Dahc.410 .\" 2. Redistributions in binary form must reproduce the above copyright
89 .Bl -column "aic7895CX" "MIPSX" "PCI/64X" "MaxSyncX" "MaxWidthX" "SCBsX" "2 3 4 5 6 7 8X"
91 .It "aic7770" Ta "10" Ta "VL" Ta "10MHz" Ta "16Bit" Ta "4" Ta "1"
92 .It "aic7850" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "8Bit" Ta "3" Ta ""
93 .It "aic7860" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "8Bit" Ta "3" Ta ""
94 .It "aic7870" Ta "10" Ta "PCI/32" Ta "10MHz" Ta "16Bit" Ta "16" Ta ""
95 .It "aic7880" Ta "10" Ta "PCI/32" Ta "20MHz" Ta "16Bit" Ta "16" Ta ""
96 .It "aic7890" Ta "20" Ta "PCI/32" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
97 .It "aic7891" Ta "20" Ta "PCI/64" Ta "40MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
98 .It "aic7892" Ta "20" Ta "PCI/64" Ta "80MHz" Ta "16Bit" Ta "16" Ta "3 4 5 6 7 8"
[all …]
H A Dsym.439 .\" 2. Redistributions in binary form must reproduce the above copyright
123 they do not involve the chip DMA FIFO and are coded on 2 DWORDs
204 .Bl -column sym53c1510d "80MHz" "Width" "SRAM" "PCI64"
206 .It "sym53c810 10MHz 8Bit N N Y"
207 .It "sym53c810a 10MHz 8Bit N N Y"
208 .It "sym53c815 10MHz 8Bit N N Y"
209 .It "sym53c825 10MHz 16Bit N N Y"
210 .It "sym53c825a 10MHz 16Bit 4KB N Y"
211 .It "sym53c860 20MHz 8Bit N N Y"
212 .It "sym53c875 20MHz 16Bit 4KB N Y"
[all …]
/freebsd/contrib/tcpdump/
H A Dprint-802_11.c8 * retain the above copyright notice and this paragraph in its entirety, (2)
40 #define IEEE802_11_FC_LEN 2
41 #define IEEE802_11_DUR_LEN 2
48 #define IEEE802_11_SEQ_LEN 2
49 #define IEEE802_11_CTL_LEN 2
50 #define IEEE802_11_CARRIED_FC_LEN 2
60 #define IEEE802_11_BCNINT_LEN 2
61 #define IEEE802_11_CAPINFO_LEN 2
62 #define IEEE802_11_LISTENINT_LEN 2
64 #define IEEE802_11_AID_LEN 2
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcpu-capacity.txt15 2 - CPU capacity definition
38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
69 #address-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Dcpu-capacity.txt15 2 - CPU capacity definition
38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
69 #address-cells = <2>;
[all …]
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drs.h14 * bandwidths <= 80MHz
16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
22 * for BPSK (MCS 0) with 2 spatial
29 IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK = BIT(2),
37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
[all...]
H A Dmac.h11 * AUX indices follows - 1 for non-CDB, 2 for CDB.
17 #define NUM_MAC_INDEX_CDB (NUM_MAC_INDEX_DRIVER + 2)
36 * @MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
88 TSF_ID_C = 2,
147 FLEXIBLE_TWT_SUPPORTED = BIT(2),
242 MAC_FILTER_ACCEPT_GRP = BIT(2),
271 * Should be a power-of-2, minus 1. Device's default is 0x0f.
273 * Should be a power-of-2, minus 1. Device's default is 0x3f.
282 * Device will automatically increase contention window by (2*CW) + 1 for each
440 #define MAX_HE_SUPP_NSS 2
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Domap-usb-host.txt29 "ohci-tll-2pin-datse0",
30 "ohci-tll-2pin-dpdm",
40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
47 * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
49 * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
[all …]
/freebsd/contrib/wpa/src/common/
H A Dieee802_11_common.c194 pos[0], pos[1], pos[2], (unsigned long) elen); in ieee802_11_parse_vendor_specific()
257 frags_len += elem->datalen + 2; in ieee802_11_fragments_length()
306 if (elen < 2 * ETH_ALEN) in ieee802_11_parse_extension()
341 if (elen < 2) in ieee802_11_parse_extension()
384 if (elen < 2) in ieee802_11_parse_extension()
488 if (elen < 2) in __ieee802_11_parse_elems()
626 if (elen < 2) in __ieee802_11_parse_elems()
632 if (elen < 2) in __ieee802_11_parse_elems()
989 while (len > 2) { in ieee802_11_parse_link_assoc_req()
999 if (2 + sub_elem_len > len) { in ieee802_11_parse_link_assoc_req()
[all …]
H A Dhw_features_common.c138 "HT40: control channel: %d (%d MHz), secondary channel: %d (%d MHz)", in allowed_ht40_channel_pair()
141 /* Verify that HT40 secondary channel is an allowed 20 MHz in allowed_ht40_channel_pair()
230 return 2; in check_40mhz_5g()
258 return 2; in check_40mhz_5g()
291 wpa_printf(MSG_DEBUG, "Found overlapping 20 MHz HT BSS: " in check_20mhz_bss()
314 affected_start = (pri_freq + sec_freq) / 2 - 25; in check_40mhz_2g4()
315 affected_end = (pri_freq + sec_freq) / 2 + 25; in check_40mhz_2g4()
316 wpa_printf(MSG_DEBUG, "40 MHz affected channel range: [%d,%d] MHz", in check_40mhz_2g4()
324 /* Check for overlapping 20 MHz BSS */ in check_40mhz_2g4()
328 "Overlapping 20 MHz BSS is found"); in check_40mhz_2g4()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos5433-tmu.dtsi27 atlas0_alert_2: atlas0-alert-2 {
56 /* Set maximum frequency as 1800MHz */
58 cooling-device = <&cpu4 1 2>, <&cpu5 1 2>,
59 <&cpu6 1 2>, <&cpu7 1 2>;
62 /* Set maximum frequency as 1700MHz */
64 cooling-device = <&cpu4 2 3>, <&cpu5 2 3>,
65 <&cpu6 2 3>, <&cpu7 2 3>;
68 /* Set maximum frequency as 1600MHz */
74 /* Set maximum frequency as 1500MHz */
80 /* Set maximum frequency as 1400MHz */
[all …]
/freebsd/contrib/wpa/src/ap/
H A Dieee802_11_ht.c115 - all STAs in the BSS are 20/40 MHz HT in 20/40 MHz BSS or
116 - all STAs in the BSS are 20 MHz HT in 20 MHz BSS
119 Set to 2 if only HT STAs are associated in BSS,
120 however and at least one 20 MHz HT STA is associated
195 affected_start = (pri_freq + sec_freq) / 2 - 25; in is_40_allowed()
196 affected_end = (pri_freq + sec_freq) / 2 + 25; in is_40_allowed()
200 wpa_printf(MSG_ERROR, "40 MHz affected channel range: [%d,%d] MHz", in is_40_allowed()
216 const u8 *data = start + IEEE80211_HDRLEN + 2; in hostapd_2040_coex_action()
229 "Ignore 20/40 BSS Coexistence Management frame since 40 MHz capability is not enabled"); in hostapd_2040_coex_action()
233 if (len < IEEE80211_HDRLEN + 2 + sizeof(*bc_ie)) { in hostapd_2040_coex_action()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5422-cpus.dtsi64 #cooling-cells = <2>; /* min followed by max */
65 capacity-dmips-mhz = <539>;
77 #cooling-cells = <2>; /* min followed by max */
78 capacity-dmips-mhz = <539>;
90 #cooling-cells = <2>; /* min followed by max */
91 capacity-dmips-mhz = <539>;
103 #cooling-cells = <2>; /* min followed by max */
104 capacity-dmips-mhz = <539>;
116 #cooling-cells = <2>; /* min followed by max */
117 capacity-dmips-mhz = <1024>;
[all …]
H A Dexynos5420-cpus.dtsi65 #cooling-cells = <2>; /* min followed by max */
66 capacity-dmips-mhz = <1024>;
77 #cooling-cells = <2>; /* min followed by max */
78 capacity-dmips-mhz = <1024>;
81 cpu2: cpu@2 {
89 #cooling-cells = <2>; /* min followed by max */
90 capacity-dmips-mhz = <1024>;
101 #cooling-cells = <2>; /* min followed by max */
102 capacity-dmips-mhz = <1024>;
113 #cooling-cells = <2>; /* min followed by max */
[all …]
/freebsd/contrib/wpa/wpa_supplicant/
H A Dop_classes.c59 * In 80 MHz, the bandwidth "spans" 12 channels (e.g., 36-48), in get_center_80mhz()
129 * In 160 MHz, the bandwidth "spans" 28 channels (e.g., 36-64), in get_center_160mhz()
199 * In 320 MHz, the bandwidth "spans" 60 channels (e.g., 65-125), in get_center_320mhz()
259 if (bw == BW40MINUS || (bw == BW40 && (((channel - 1) / 4) % 2))) { in verify_channel()
275 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
276 * result and use only the 80 MHz specific version. in verify_channel()
282 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
283 * result and use only the 160 MHz specific version. in verify_channel()
289 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
290 * result and use only the 80 MHz specific version. in verify_channel()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Darmada3700-periph-clock.txt17 2 sec_at Security AT
24 9 i2c_2 I2C 2
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
47 11 usb32-sub2-sys USB 2 clock
68 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
H A Dmaxim,max9485.txt5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
8 - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
10 MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
15 - clocks: Input clock, must provide 27.000 MHz
34 xo-27mhz: xo-27mhz {
45 clocks = <&xo-27mhz>;
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3288-veyron-mickey.dts86 * and don't let the GPU go faster than 400 MHz.
106 * - 800 MHz (hot)
107 * - 800 MHz - 696 MHz (hotter)
108 * - 696 MHz - min (very hot)
111 * - 800 MHz appears to be a "sweet spot" for me. I can run
113 * - After 696 MHz we stop lowering voltage, so throttling
139 /* At very hot, don't let GPU go over 300 MHz */
142 cooling-device = <&gpu 2 2>;
180 /* After 1st level throttle the GPU down to as low as 400 MHz */
200 /* When hot, GPU goes down to 300 MHz */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-g12b.dtsi51 capacity-dmips-mhz = <592>;
53 #cooling-cells = <2>;
61 capacity-dmips-mhz = <592>;
63 #cooling-cells = <2>;
71 capacity-dmips-mhz = <1024>;
73 #cooling-cells = <2>;
81 capacity-dmips-mhz = <1024>;
83 #cooling-cells = <2>;
91 capacity-dmips-mhz = <1024>;
93 #cooling-cells = <2>;
[all …]
H A Dmeson-gxm.dtsi46 capacity-dmips-mhz = <1024>;
50 capacity-dmips-mhz = <1024>;
53 cpu2: cpu@2 {
54 capacity-dmips-mhz = <1024>;
58 capacity-dmips-mhz = <1024>;
66 capacity-dmips-mhz = <1024>;
69 #cooling-cells = <2>;
77 capacity-dmips-mhz = <1024>;
80 #cooling-cells = <2>;
88 capacity-dmips-mhz = <1024>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt6002.dtsi5 * Other names: H13J, "Jade 2C"
22 #address-cells = <2>;
23 #size-cells = <2>;
77 capacity-dmips-mhz = <714>;
91 capacity-dmips-mhz = <714>;
105 capacity-dmips-mhz = <1024>;
119 capacity-dmips-mhz = <1024>;
133 capacity-dmips-mhz = <1024>;
147 capacity-dmips-mhz = <1024>;
161 capacity-dmips-mhz = <1024>;
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx6_anatop.c2 * SPDX-License-Identifier: BSD-2-Clause
13 * 2. Redistributions in binary form must reproduce the above copyright
88 struct resource *res[2];
119 * 396MHz, it also says that the ARM and SOC voltages can't differ by
124 uint32_t mhz; member
136 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked
234 return ((sc->refosc_mhz * (plldiv / 2)) / (corediv + 1)); in cpufreq_mhz_from_div()
243 *plldiv = ((*corediv + 1) * cpu_mhz) / (sc->refosc_mhz / 2); in cpufreq_mhz_to_div()
266 d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz); in cpufreq_nearest_oppt()
281 if (op->mhz > sc->cpu_curmhz) { in cpufreq_set_clock()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dsony,imx415.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
18 available via CSI-2 serial data output (two or four lanes).
31 description: Input clock (24 MHz, 27 MHz, 37.125 MHz, 72 MHz or 74.25 MHz)
61 - const: 2
64 - const: 2
101 orientation = <2>;
108 data-lanes = <1 2 3 4>;
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dintegratorcp.dts49 /* The codec chrystal operates at 24.576 MHz */
56 /* The chrystal is divided by 2 by the codec for the AACI bit clock */
60 clock-div = <2>;
65 /* This is a 25MHz chrystal on the base board */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
124 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
133 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
149 /* TIMER0 runs directly on the 25MHz chrystal */
155 /* TIMER1 runs @ 1MHz */
[all …]

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