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/linux/Documentation/devicetree/bindings/phy/
H A Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
11 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
27 - apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit)
39 - apm,tx-pre-cursor2 : 2nd pre-cursor emphasis taps control. Two set of
48 0 = 1-2Gbps
49 1 = 2-4Gbps (1st tuple default)
50 2 = 4-8Gbps
51 3 = 8-15Gbps (2nd tuple default)
52 4 = 2.5-4Gbps
[all …]
H A Dmediatek,hdmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
56 TX DRV bias current for < 1.65Gbps
64 TX DRV bias current for >= 1.65Gbps
/linux/drivers/scsi/mvsas/
H A Dmv_94xx.h122 VSR_PHY_MODE10 = 0x0A * 4, /* Event Counter 2 */
143 MVS_IRQ_COM_IN_I2O_IOP2 = (1 << 2),
180 * bit 2: 6Gbps support
181 * bit 1: 3Gbps support
182 * bit 0: 1.5Gbps support
188 * bit 5: G1 (1.5Gbps) Without SSC
189 * bit 4: G1 (1.5Gbps) with SSC
190 * bit 3: G2 (3.0Gbps) Without SSC
191 * bit 2: G2 (3.0Gbps) with SSC
192 * bit 1: G3 (6.0Gbps) without SSC
[all …]
/linux/Documentation/scsi/
H A Dbfa.rst16 1657:0013:1657:0014 425 4Gbps dual port FC HBA
17 1657:0013:1657:0014 825 8Gbps PCIe dual port FC HBA
18 1657:0013:103c:1742 HP 82B 8Gbps PCIedual port FC HBA
19 1657:0013:103c:1744 HP 42B 4Gbps dual port FC HBA
20 1657:0017:1657:0014 415 4Gbps single port FC HBA
21 1657:0017:1657:0014 815 8Gbps single port FC HBA
22 1657:0017:103c:1741 HP 41B 4Gbps single port FC HBA
23 1657:0017:103c 1743 HP 81B 8Gbps single port FC HBA
24 1657:0021:103c:1779 804 8Gbps FC HBA for HP Bladesystem c-class
26 1657:0014:1657:0014 1010 10Gbps single port CNA - FCOE
[all …]
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dp_types.h35 LANE_COUNT_TWO = 2,
50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane
55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane
57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane
58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_arcturus.h37 #define NUM_MP0CLK_DPM_LEVELS 2
41 #define NUM_XGMI_LEVELS 2
58 #define FEATURE_DPM_UCLK_BIT 2
189 #define THROTTLER_TEMP_HOTSPOT_BIT 2
214 #define WORKLOAD_PPLIB_VIDEO_BIT 2
265 uint8_t Padding[2];
429 XGMI_LINK_RATE_2 = 2, // 2Gbps
430 XGMI_LINK_RATE_4 = 4, // 4Gbps
431 XGMI_LINK_RATE_8 = 8, // 8Gbps
432 XGMI_LINK_RATE_12 = 12, // 12Gbps
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h35 #define NUM_SMNCLK_DPM_LEVELS 2
37 #define NUM_MP0CLK_DPM_LEVELS 2
46 #define NUM_MP1CLK_DPM_LEVELS 2
47 #define NUM_LINK_LEVELS 2
49 #define NUM_XGMI_LEVELS 2
72 #define PPSMC_GeminiModeSlave 2 //Slave GPU on a Gemini board
78 #define FEATURE_DPM_GFX_GPO_BIT 2
197 #define THROTTLER_TEMP_HOTSPOT_BIT 2
221 #define FW_DSTATE_G6_PHY_VDDCI_OFF_BIT 2
264 #define LED_DISPLAY_ERROR_BIT 2
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/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
65 #define CFG_0_TX_FC_EN_SHIFT 2
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
125 #define CFG_3_RX_CBFC_REDIR_EN_SHIFT 2
/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.c87 * - PHY, Clock and Mode setup for 2k && 4k modes
121 MESON_VENC_SOURCE_ENCP = 2,
185 return readl(dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2)); in dw_hdmi_g12a_top_read()
208 writel(data, dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2)); in dw_hdmi_g12a_top_write()
286 if (mode_is_420) pixel_clock /= 2; in meson_hdmi_phy_setup_mode()
291 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
295 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
299 /* 1.485Gbps */ in meson_hdmi_phy_setup_mode()
310 /* 5.94Gbps, 3.7125Gbps */ in meson_hdmi_phy_setup_mode()
314 /* 2.97Gbps */ in meson_hdmi_phy_setup_mode()
[all …]
/linux/drivers/scsi/be2iscsi/
H A DKconfig3 tristate "Emulex 10Gbps iSCSI - BladeEngine 2"
11 10Gbps Storage adapter - BladeEngine 2.
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dmaxim,max96717.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 title: MAX96717 CSI-2 to GMSL2 Serializer
14 The MAX96717 serializer converts MIPI CSI-2 D-PHY formatted input
25 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
27 MAX96717F only supports a fixed rate of 3Gbps in the forward direction.
39 const: 2
59 description: CSI-2 Input port
113 #gpio-cells = <2>;
123 data-lanes = <1 2 3 4>;
149 data-lanes = <1 2 3 4>;
H A Dmaxim,max96714.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 title: Maxim MAX96714 GMSL2 to CSI-2 Deserializer
15 CSI-2 D-PHY formatted output. The device allows the GMSL2 link to
23 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
25 MAX96714F only supports a fixed rate of 3Gbps in the forward direction.
62 description: CSI-2 Output port
132 data-lanes = <1 2 3 4>;
147 #gpio-cells = <2>;
157 data-lanes = <1 2>;
H A Dsony,imx214.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
15 interface. Image data is sent through MIPI CSI-2, through 2 or 4 lanes at a
16 maximum throughput of 1.2Gbps/lane.
68 - const: 2
71 - const: 2
117 data-lanes = <1 2 3 4>;
/linux/tools/testing/selftests/drivers/net/mlxsw/
H A Dqos_lib.sh29 # 1Gbps. That wouldn't saturate egress and MC would thus get through,
30 # seemingly winning bandwidth on account of UC. Demand at least 2Gbps
/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_main.h28 #define HCLGE_RD_FIRST_STATS_NUM 2
89 #define HCLGE_RSS_TC_SIZE_1 2
138 #define HCLGE_PF_ID_M GENMASK(2, 0)
152 #define HCLGE_IMP_RESET_BIT 2
183 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)
189 #define HCLGE_SUPPORT_25G_BIT BIT(2)
247 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
248 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
249 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
250 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
[all …]
/linux/fs/smb/client/
H A Dcifs_debug.c180 return "1Gbps"; in smb_speed_to_str()
182 return "2.5Gbps"; in smb_speed_to_str()
184 return "5Gbps"; in smb_speed_to_str()
186 return "10Gbps"; in smb_speed_to_str()
188 return "14Gbps"; in smb_speed_to_str()
190 return "20Gbps"; in smb_speed_to_str()
192 return "25Gbps"; in smb_speed_to_str()
194 return "40Gbps"; in smb_speed_to_str()
196 return "50Gbps"; in smb_speed_to_str()
198 return "56Gbps"; in smb_speed_to_str()
[all …]
/linux/include/rdma/
H A Dopa_port_info.h16 #define OPA_PORT_PACKET_FORMAT_9B 2 /* Format 9B */
22 #define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */
29 #define OPA_LINKDOWN_REASON_BAD_PKT_LEN 2
90 #define OPA_LINKINIT_REASON_FLAPPING (2 << 4)
96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
97 #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
98 #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
111 /* reserved (1 << 2) */
118 OPA_PORT_PHYS_CONF_FIXED = 2,
146 /* Filter Raw In/Out bits 1 and 2 were removed */
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c27 for ((__lane) = 0; (__lane) < 2; (__lane)++) \
68 return intel_tc_port_max_lane_count(dig_port) > 2 in intel_cx0_get_owned_lane_mask()
440 return 2; in intel_c10_get_tx_term_ctl()
484 int lane = ln / 2; in intel_cx0_phy_set_signal_levels()
485 int tx = ln % 2; in intel_cx0_phy_set_signal_levels()
499 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 2), in intel_cx0_phy_set_signal_levels()
530 .pll[2] = 0x30,
556 .pll[2] = 0xA2,
582 .pll[2] = 0xDA,
608 .pll[2] = 0xF8,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_capability.c141 case 0x40: // 2 lttpr repeaters in dp_parse_lttpr_repeater_count()
142 return 2; in dp_parse_lttpr_repeater_count()
184 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation. in linkRateInKHzToLinkRateMultiplier()
187 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
190 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
193 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
196 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
199 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2)- 3.24 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
202 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
205 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2)- 5.40 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
[all …]
H A Dlink_dp_dpia_bw.c71 #define BW_GRANULARITY_0 4 // 0.25 Gbps
72 #define BW_GRANULARITY_1 2 // 0.5 Gbps
73 #define BW_GRANULARITY_2 1 // 1 Gbps
92 case 2: in get_bw_granularity()
204 hr_index_temp = (dc->links[i]->link_index - lowest_dpia_index) / 2; in get_host_router_total_dp_tunnel_bw()
392 * 2. Due to the fact that DP-Tx tried to allocated ESTIMATED BW and failed then in dpia_handle_bw_alloc_response()
460 //2. Cold Unplug in dpia_handle_usb4_bandwidth_allocation_for_link()
522 hr_index = (link[i]->link_index - lowest_dpia_index) / 2; in dpia_validate_usb4_bw()
/linux/drivers/usb/host/
H A Dxhci-hub.c26 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
27 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
28 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
29 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
30 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
31 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
32 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
33 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
89 ssic = (ssac + 1) / 2 - 1; in xhci_create_usb3x_bos_desc()
170 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */ in xhci_create_usb3x_bos_desc()
[all …]
/linux/Documentation/networking/device_drivers/ethernet/pensando/
H A Dionic.rst36 ionic 0000:b5:00.0 enp181s0: Link up - 100 Gbps
39 ionic 0000:b6:00.0 enp182s0: Link up - 100 Gbps
170 rx_0_pkts: 2
233 frames_tx_broadcast: 2
/linux/Documentation/driver-api/
H A Dinterconnect.rst133 # Set desired BW to 1GBps avg and 2GBps peak.
/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-board.c10 * it under the terms of the GNU General Public License, Version 2, as
108 /* Board has 2 management ports */ in cvmx_helper_board_get_mii_address()
110 (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2))) in cvmx_helper_board_get_mii_address()
114 * ports MII0 = 0, MII1 = 1, SGMII = 2-5. in cvmx_helper_board_get_mii_address()
117 return ipd_port + 2; in cvmx_helper_board_get_mii_address()
128 * to a switch, and 2 loop to each other in cvmx_helper_board_get_mii_address()
135 if (ipd_port == 2) in cvmx_helper_board_get_mii_address()
173 if (ipd_port >= 0 && ipd_port <= 2) in cvmx_helper_board_get_mii_address()
221 /* The simulator gives you a simulated 1Gbps full duplex link */ in __cvmx_helper_board_link_get()
253 case 2: /* 1 Gbps */ in __cvmx_helper_board_link_get()
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dmicrochip,usb5744.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
15 controller, so 5 Gbps SuperSpeed data transfers are not affected by slower
84 hub: usb-hub@2d {
103 /* 3.0 hub on port 2 */
104 hub_3_0: hub@2 {
106 reg = <2>;

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