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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsamsung,exynos850-clock.yaml20 two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
73 - description: External reference clock (26 MHz)
89 - description: External reference clock (26 MHz)
107 - description: External reference clock (26 MHz)
125 - description: External reference clock (26 MHz)
143 - description: External reference clock (26 MHz)
167 - description: External reference clock (26 MHz)
187 - description: External reference clock (26 MHz)
207 - description: External reference clock (26 MHz)
225 - description: External reference clock (26 MHz)
[all …]
H A Dsamsung,exynosautov9-clock.yaml20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
71 - description: External reference clock (26 MHz)
87 - description: External reference clock (26 MHz)
105 - description: External reference clock (26 MHz)
123 - description: External reference clock (26 MHz)
141 - description: External reference clock (26 MHz)
161 - description: External reference clock (26 MHz)
183 - description: External reference clock (26 MHz)
205 - description: External reference clock (26 MHz)
225 - description: External reference clock (26 MHz)
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H A Dsamsung,exynos7885-clock.yaml20 is an external clock: OSCCLK (26 MHz). This external clock must be defined
64 - description: External reference clock (26 MHz)
80 - description: External reference clock (26 MHz)
102 - description: External reference clock (26 MHz)
128 - description: External reference clock (26 MHz)
H A Dnvidia,tegra20-car.yaml21 (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
H A Dnvidia,tegra124-car.yaml21 (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
H A Dst,stm32mp25-rcc.yaml36 - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)
37 - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)
38 - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
69 - description: CK_SCMI_FLEXGEN_26 flexgen clock 26
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drs.h16 * bandwidths <= 80MHz
18 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
39 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
42 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
43 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
124 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
125 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
148 * <nss, channel-width> pair (0 - 80mhz width and below, 1 - 160mhz).
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H A Dsta.h37 * will send all the frames in 20MHz even when FAT channel is requested.
38 * @STA_FLG_FAT_EN_20MHZ: no wide channels are supported, only 20 MHz
39 * @STA_FLG_FAT_EN_40MHZ: wide channels up to 40 MHz supported
40 * @STA_FLG_FAT_EN_80MHZ: wide channels up to 80 MHz supported
41 * @STA_FLG_FAT_EN_160MHZ: wide channels up to 160 MHz supported
87 STA_FLG_FAT_EN_20MHZ = (0 << 26),
88 STA_FLG_FAT_EN_40MHZ = (1 << 26),
89 STA_FLG_FAT_EN_80MHZ = (2 << 26),
90 STA_FLG_FAT_EN_160MHZ = (3 << 26),
91 STA_FLG_FAT_EN_MSK = (3 << 26),
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dmax8952.txt15 - 0: 26 MHz
16 - 1: 13 MHz
17 - 2: 19.2 MHz
18 Defaults to 26 MHz if not specified.
H A Dmaxim,max8952.yaml62 - 0: 26 MHz
63 - 1: 13 MHz
64 - 2: 19.2 MHz
65 Defaults to 26 MHz if not specified.
/freebsd/sys/dev/bwn/
H A Dif_bwn_phy_common.c95 case BHND_PMU_SPURAVOID_M2: /* 168 Mhz: 2^26/168 = 0x61862 */ in bwn_mac_switch_freq()
99 case BHND_PMU_SPURAVOID_M1: /* 164 Mhz: 2^26/164 = 0x63e70 */ in bwn_mac_switch_freq()
103 case BHND_PMU_SPURAVOID_NONE: /* 160 Mhz: 2^26/160 = 0x66666 */ in bwn_mac_switch_freq()
116 case BHND_PMU_SPURAVOID_M2: /* 126 Mhz */ in bwn_mac_switch_freq()
120 case BHND_PMU_SPURAVOID_M1: /* 123 Mhz */ in bwn_mac_switch_freq()
124 case BHND_PMU_SPURAVOID_NONE: /* 120 Mhz */ in bwn_mac_switch_freq()
135 case BHND_PMU_SPURAVOID_M1: /* 82 Mhz */ in bwn_mac_switch_freq()
139 case BHND_PMU_SPURAVOID_NONE: /* 80 Mhz */ in bwn_mac_switch_freq()
/freebsd/sys/contrib/device-tree/Bindings/ufs/
H A Dufshcd-pltfrm.txt45 specification allows host to provide one of the 4 frequencies (19.2 MHz,
46 26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is
48 Defaults to 26 MHz(as per specification) if not specified by host.
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dintegratorcp.dts49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
124 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
133 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
149 /* TIMER0 runs directly on the 25MHz chrystal */
155 /* TIMER1 runs @ 1MHz */
161 /* TIMER2 runs @ 1MHz */
179 /* The SIC is cascaded off IRQ 26 on the PIC */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dmediatek,xsphy.yaml68 mediatek,src-ref-clk-mhz:
71 default: 26
94 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
176 mediatek,src-ref-clk-mhz = <26>;
H A Dphy-mtk-xsphy.txt21 - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
36 "ref": 48M reference clock for HighSpeed analog phy; and 26M
88 mediatek,src-ref-clk-mhz = <26>;
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dtoshiba,tc358767.txt8 clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.
H A Dti,sn65dsi86.txt29 clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
H A Dtoshiba,tc358767.yaml40 clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.
H A Dti,sn65dsi86.yaml56 be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi-mt65xx.txt30 - <&clk26m>: specify parent clock 26MHZ.
31 - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
33 - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
34 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
35 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dstmpe.txt28 0 -> 1.625 MHz 2 || 3 -> 6.5 MHz
29 1 -> 3.25 MHz
36 interrupts = <26 0x4>;
/freebsd/share/man/man4/
H A Dsym.457 .Dd December 26, 2020
204 .Bl -column sym53c1510d "80MHz" "Width" "SRAM" "PCI64"
206 .It "sym53c810 10MHz 8Bit N N Y"
207 .It "sym53c810a 10MHz 8Bit N N Y"
208 .It "sym53c815 10MHz 8Bit N N Y"
209 .It "sym53c825 10MHz 16Bit N N Y"
210 .It "sym53c825a 10MHz 16Bit 4KB N Y"
211 .It "sym53c860 20MHz 8Bit N N Y"
212 .It "sym53c875 20MHz 16Bit 4KB N Y"
213 .It "sym53c876 20MHz 16Bit 4KB N Y"
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/freebsd/sys/cddl/dev/dtrace/powerpc/
H A Ddtrace_subr.c134 * lower than x86, the scale shift is 26 instead of 28, allowing for a 15.63MHz
137 #define SCALE_SHIFT 26
164 * Thus minimum supported Timebase frequency is 15.63MHz. in dtrace_gethrtime_init()
171 * 2^26 factor was chosen quite arbitrarily from practical in dtrace_gethrtime_init()
173 * - it supports TSC frequencies as low as 15.63MHz (see above); in dtrace_gethrtime_init()
/freebsd/contrib/wpa/src/common/
H A Dhw_features_common.c138 "HT40: control channel: %d (%d MHz), secondary channel: %d (%d MHz)", in allowed_ht40_channel_pair()
141 /* Verify that HT40 secondary channel is an allowed 20 MHz in allowed_ht40_channel_pair()
291 wpa_printf(MSG_DEBUG, "Found overlapping 20 MHz HT BSS: " in check_20mhz_bss()
316 wpa_printf(MSG_DEBUG, "40 MHz affected channel range: [%d,%d] MHz", in check_40mhz_2g4()
324 /* Check for overlapping 20 MHz BSS */ in check_40mhz_2g4()
328 "Overlapping 20 MHz BSS is found"); in check_40mhz_2g4()
352 "40 MHz pri/sec mismatch with BSS " in check_40mhz_2g4()
373 "40 MHz Intolerant is set on channel %d in BSS " in check_40mhz_2g4()
449 /* TODO: 320 MHz */ in punct_update_legacy_bw()
547 "6 GHz 80+80 MHz configuration doesn't use valid 80 MHz channels"); in hostapd_set_freq_params()
[all …]
/freebsd/sys/contrib/dev/athk/ath10k/
H A Drx_desc.h39 RX_ATTENTION_FLAGS_BUFFER_FRAGMENT = BIT(26),
766 * RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
770 * RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth.
774 * RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth.
778 * RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth.
782 * RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
786 * RSSI of RX PPDU on chain 1 of secondary 20 MHz bandwidth.
790 * RSSI of RX PPDU on chain 1 of secondary 40 MHz bandwidth.
794 * RSSI of RX PPDU on chain 1 of secondary 80 MHz bandwidth.
798 * RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth.
[all …]

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